techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 #define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
  29                              // to one LUT6 (instead of a LUT5 + LUT2)
  30
  31 struct SynthXilinxPass : public ScriptPass
  32 {
  33         SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  34
  35         void help() YS_OVERRIDE
  36         {
  37                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  38                 log("\n");
  39                 log("    synth_xilinx [options]\n");
  40                 log("\n");
  41                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  42                 log("partly selected designs. At the moment this command creates netlists that are\n");
  43                 log("compatible with 7-Series Xilinx devices.\n");
  44                 log("\n");
  45                 log("    -top <module>\n");
  46                 log("        use the specified module as top module\n");
  47                 log("\n");
  48                 log("    -family {xcup|xcu|xc7|xc6s}\n");
  49                 log("        run synthesis for the specified Xilinx architecture\n");
  50                 log("        generate the synthesis netlist for the specified family.\n");
  51                 log("        default: xc7\n");
  52                 log("\n");
  53                 log("    -edif <file>\n");
  54                 log("        write the design to the specified edif file. writing of an output file\n");
  55                 log("        is omitted if this parameter is not specified.\n");
  56                 log("\n");
  57                 log("    -blif <file>\n");
  58                 log("        write the design to the specified BLIF file. writing of an output file\n");
  59                 log("        is omitted if this parameter is not specified.\n");
  60                 log("\n");
  61                 log("    -vpr\n");
  62                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  63                 log("        (this feature is experimental and incomplete)\n");
  64                 log("\n");
  65                 log("    -nocarry\n");
  66                 log("        disable inference of carry chains\n");
  67                 log("\n");
  68                 log("    -nobram\n");
  69                 log("        disable inference of block rams\n");
  70                 log("\n");
  71                 log("    -nodram\n");
  72                 log("        disable inference of distributed rams\n");
  73                 log("\n");
  74                 log("    -nosrl\n");
  75                 log("        disable inference of shift registers\n");
  76                 log("\n");
  77                 log("    -nocarry\n");
  78                 log("        do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
  79                 log("\n");
  80                 log("    -nowidelut\n");
  81                 log("        do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
  82                 log("\n");
  83                 log("    -run <from_label>:<to_label>\n");
  84                 log("        only run the commands between the labels (see below). an empty\n");
  85                 log("        from label is synonymous to 'begin', and empty to label is\n");
  86                 log("        synonymous to the end of the command list.\n");
  87                 log("\n");
  88                 log("    -flatten\n");
  89                 log("        flatten design before synthesis\n");
  90                 log("\n");
  91                 log("    -retime\n");
  92                 log("        run 'abc' with -dff option\n");
  93                 log("\n");
  94                 log("    -abc9\n");
  95                 log("        use new ABC9 flow (EXPERIMENTAL)\n");
  96                 log("\n");
  97                 log("\n");
  98                 log("The following commands are executed by this synthesis command:\n");
  99                 help_script();
 100                 log("\n");
 101         }
 102
 103         std::string top_opt, edif_file, blif_file, family;
 104         bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
 105
 106         void clear_flags() YS_OVERRIDE
 107         {
 108                 top_opt = "-auto-top";
 109                 edif_file.clear();
 110                 blif_file.clear();
 111                 family = "xc7";
 112                 flatten = false;
 113                 retime = false;
 114                 vpr = false;
 115                 nocarry = false;
 116                 nobram = false;
 117                 nodram = false;
 118                 nosrl = false;
 119                 nocarry = false;
 120                 nowidelut = false;
 121                 abc9 = false;
 122         }
 123
 124         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 125         {
 126                 std::string run_from, run_to;
 127                 clear_flags();
 128
 129                 size_t argidx;
 130                 for (argidx = 1; argidx < args.size(); argidx++)
 131                 {
 132                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 133                                 top_opt = "-top " + args[++argidx];
 134                                 continue;
 135                         }
 136                         if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
 137                                 family = args[++argidx];
 138                                 continue;
 139                         }
 140                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 141                                 edif_file = args[++argidx];
 142                                 continue;
 143                         }
 144                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 145                                 blif_file = args[++argidx];
 146                                 continue;
 147                         }
 148                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 149                                 size_t pos = args[argidx+1].find(':');
 150                                 if (pos == std::string::npos)
 151                                         break;
 152                                 run_from = args[++argidx].substr(0, pos);
 153                                 run_to = args[argidx].substr(pos+1);
 154                                 continue;
 155                         }
 156                         if (args[argidx] == "-flatten") {
 157                                 flatten = true;
 158                                 continue;
 159                         }
 160                         if (args[argidx] == "-retime") {
 161                                 retime = true;
 162                                 continue;
 163                         }
 164                         if (args[argidx] == "-nocarry") {
 165                                 nocarry = true;
 166                                 continue;
 167                         }
 168                         if (args[argidx] == "-nowidelut") {
 169                                 nowidelut = true;
 170                                 continue;
 171                         }
 172                         if (args[argidx] == "-vpr") {
 173                                 vpr = true;
 174                                 continue;
 175                         }
 176                         if (args[argidx] == "-nocarry") {
 177                                 nocarry = true;
 178                                 continue;
 179                         }
 180                         if (args[argidx] == "-nobram") {
 181                                 nobram = true;
 182                                 continue;
 183                         }
 184                         if (args[argidx] == "-nodram") {
 185                                 nodram = true;
 186                                 continue;
 187                         }
 188                         if (args[argidx] == "-nosrl") {
 189                                 nosrl = true;
 190                                 continue;
 191                         }
 192                         if (args[argidx] == "-abc9") {
 193                                 abc9 = true;
 194                                 continue;
 195                         }
 196                         break;
 197                 }
 198                 extra_args(args, argidx, design);
 199
 200                 if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
 201                         log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
 202
 203                 if (!design->full_selection())
 204                         log_cmd_error("This command only operates on fully selected designs!\n");
 205
 206                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 207                 log_push();
 208
 209                 run_script(design, run_from, run_to);
 210
 211                 log_pop();
 212         }
 213
 214         void script() YS_OVERRIDE
 215         {
 216                 if (check_label("begin")) {
 217                         if (vpr)
 218                                 run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 219                         else
 220                                 run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
 221
 222                         run("read_verilog -lib +/xilinx/cells_xtra.v");
 223
 224                         if (!nobram || help_mode)
 225                                 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
 226
 227                         run(stringf("hierarchy -check %s", top_opt.c_str()));
 228                 }
 229
 230                 if (check_label("flatten", "(with '-flatten' only)")) {
 231                         if (flatten || help_mode) {
 232                                 run("proc");
 233                                 run("flatten");
 234                         }
 235                 }
 236
 237                 if (check_label("coarse")) {
 238                         run("synth -run coarse");
 239
 240                         // shregmap -tech xilinx can cope with $shiftx and $mux
 241                         //   cells for identifying variable-length shift registers,
 242                         //   so attempt to convert $pmux-es to the former
 243                         if (!nosrl || help_mode)
 244                                 run("pmux2shiftx", "(skip if '-nosrl')");
 245
 246                         // Run a number of peephole optimisations, including one
 247                         //   that optimises $mul cells driving $shiftx's B input
 248                         //   and that aids wide mux analysis
 249                         run("peepopt");
 250                 }
 251
 252                 if (check_label("bram", "(skip if '-nobram')")) {
 253                         if (!nobram || help_mode) {
 254                                 run("memory_bram -rules +/xilinx/brams.txt");
 255                                 run("techmap -map +/xilinx/brams_map.v");
 256                         }
 257                 }
 258
 259                 if (check_label("dram", "(skip if '-nodram')")) {
 260                         if (!nodram || help_mode) {
 261                                 run("memory_bram -rules +/xilinx/drams.txt");
 262                                 run("techmap -map +/xilinx/drams_map.v");
 263                         }
 264                 }
 265
 266                 if (check_label("fine")) {
 267                         run("opt -fast -full");
 268                         run("memory_map");
 269                         run("dffsr2dff");
 270                         run("dff2dffe");
 271                         run("opt -full");
 272
 273                         if (!nosrl || help_mode) {
 274                                 // shregmap operates on bit-level flops, not word-level,
 275                                 //   so break those down here
 276                                 run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
 277                                 // shregmap with '-tech xilinx' infers variable length shift regs
 278                                 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 279                         }
 280
 281                         std::string techmap_files = " -map +/techmap.v";
 282                         if (help_mode)
 283                                 techmap_files += " [-map +/xilinx/arith_map.v]";
 284                         else if (!nocarry) {
 285                                 techmap_files += " -map +/xilinx/arith_map.v";
 286                                 if (vpr)
 287                                         techmap_files += " -D _EXPLICIT_CARRY";
 288                                 else if (abc9)
 289                                         techmap_files += " -D _CLB_CARRY";
 290                         }
 291                         run("techmap " + techmap_files);
 292                         run("opt -fast");
 293                 }
 294
 295                 if (check_label("map_cells")) {
 296                         run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 297                         run("clean");
 298                 }
 299
 300                 if (check_label("map_luts")) {
 301                         run("opt_expr -mux_undef");
 302                         if (help_mode)
 303                                 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
 304                         else if (abc9) {
 305                                 if (family != "xc7")
 306                                         log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 307                                 if (nowidelut)
 308                                         run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
 309                                 else
 310                                         run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
 311                         }
 312                         else {
 313                                 if (nowidelut)
 314                                         run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 315                                 else
 316                                         run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 317                         }
 318                         run("clean");
 319
 320                         // This shregmap call infers fixed length shift registers after abc
 321                         //   has performed any necessary retiming
 322                         if (!nosrl || help_mode)
 323                                 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 324                         run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 325                         run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 326                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 327                         run("clean");
 328                 }
 329
 330                 if (check_label("check")) {
 331                         run("hierarchy -check");
 332                         run("stat -tech xilinx");
 333                         run("check -noinit");
 334                 }
 335
 336                 if (check_label("edif")) {
 337                         if (!edif_file.empty() || help_mode)
 338                                 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
 339                 }
 340
 341                 if (check_label("blif")) {
 342                         if (!blif_file.empty() || help_mode)
 343                                 run(stringf("write_blif %s", edif_file.c_str()));
 344                 }
 345         }
 346 } SynthXilinxPass;
 347
 348 PRIVATE_NAMESPACE_END