2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 bool check_label(bool &active
, std::string run_from
, std::string run_to
, std::string label
)
30 if (label
== run_from
)
37 struct SynthXilinxPass
: public Pass
{
38 SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
41 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
43 log(" synth_xilinx [options]\n");
45 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
46 log("partly selected designs. At the moment this command creates netlists that are\n");
47 log("compatible with 7-series and 6-series Xilinx devices.\n");
49 log(" -top <module>\n");
50 log(" use the specified module as top module (default='top')\n");
52 log(" -edif <file>\n");
53 log(" write the design to the specified edif file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
56 log(" -run <from_label>:<to_label>\n");
57 log(" only run the commands between the labels (see below). an empty\n");
58 log(" from label is synonymous to 'begin', and empty to label is\n");
59 log(" synonymous to the end of the command list.\n");
62 log("The following commands are executed by this synthesis command:\n");
65 log(" hierarchy -check -top <top>\n");
68 log(" synth -run coarse\n");
71 log(" memory_bram -rules +/xilinx/brams.txt\n");
72 log(" techmap -map +/xilinx/brams.v\n");
75 log(" synth -run fine\n");
78 log(" abc -lut 6:8\n");
82 log(" techmap -map +/xilinx/cells.v\n");
86 log(" write_edif synth.edif\n");
89 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
91 std::string top_module
= "top";
92 std::string arch_name
= "spartan6";
93 std::string edif_file
;
94 std::string run_from
, run_to
;
97 for (argidx
= 1; argidx
< args
.size(); argidx
++)
99 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
100 top_module
= args
[++argidx
];
103 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
104 edif_file
= args
[++argidx
];
107 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
108 size_t pos
= args
[argidx
+1].find(':');
109 if (pos
== std::string::npos
)
111 run_from
= args
[++argidx
].substr(0, pos
);
112 run_to
= args
[argidx
].substr(pos
+1);
117 extra_args(args
, argidx
, design
);
119 if (!design
->full_selection())
120 log_cmd_error("This comannd only operates on fully selected designs!\n");
122 bool active
= run_from
.empty();
124 log_header("Executing SYNTH_XILINX pass.\n");
127 if (check_label(active
, run_from
, run_to
, "begin"))
129 Pass::call(design
, stringf("hierarchy -check -top %s", top_module
.c_str()));
132 if (check_label(active
, run_from
, run_to
, "coarse"))
134 Pass::call(design
, "synth -run coarse");
137 if (check_label(active
, run_from
, run_to
, "bram"))
139 Pass::call(design
, "memory_bram -rules +/xilinx/brams.txt");
140 Pass::call(design
, "techmap -map +/xilinx/brams.v");
143 if (check_label(active
, run_from
, run_to
, "fine"))
145 Pass::call(design
, "synth -run fine");
148 if (check_label(active
, run_from
, run_to
, "map_luts"))
150 Pass::call(design
, "abc -lut 6:8");
151 Pass::call(design
, "clean");
154 if (check_label(active
, run_from
, run_to
, "map_cells"))
156 Pass::call(design
, "techmap -map +/xilinx/cells.v");
157 Pass::call(design
, "clean");
160 if (check_label(active
, run_from
, run_to
, "edif"))
162 if (!edif_file
.empty())
163 Pass::call(design
, stringf("write_edif %s", edif_file
.c_str()));
170 PRIVATE_NAMESPACE_END