techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
  29 {
  30         if (label == run_from)
  31                 active = true;
  32         if (label == run_to)
  33                 active = false;
  34         return active;
  35 }
  36
  37 struct SynthXilinxPass : public Pass {
  38         SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  39         virtual void help()
  40         {
  41                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  42                 log("\n");
  43                 log("    synth_xilinx [options]\n");
  44                 log("\n");
  45                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  46                 log("partly selected designs. At the moment this command creates netlists that are\n");
  47                 log("compatible with 7-Series Xilinx devices.\n");
  48                 log("\n");
  49                 log("    -top <module>\n");
  50                 log("        use the specified module as top module (default='top')\n");
  51                 log("\n");
  52                 log("    -edif <file>\n");
  53                 log("        write the design to the specified edif file. writing of an output file\n");
  54                 log("        is omitted if this parameter is not specified.\n");
  55                 log("\n");
  56                 log("    -run <from_label>:<to_label>\n");
  57                 log("        only run the commands between the labels (see below). an empty\n");
  58                 log("        from label is synonymous to 'begin', and empty to label is\n");
  59                 log("        synonymous to the end of the command list.\n");
  60                 log("\n");
  61                 log("    -flatten\n");
  62                 log("        flatten design before synthesis\n");
  63                 log("\n");
  64                 log("    -retime\n");
  65                 log("        run 'abc' with -dff option\n");
  66                 log("\n");
  67                 log("\n");
  68                 log("The following commands are executed by this synthesis command:\n");
  69                 log("\n");
  70                 log("    begin:\n");
  71                 log("        read_verilog -lib +/xilinx/cells_sim.v\n");
  72                 log("        hierarchy -check -top <top>\n");
  73                 log("\n");
  74                 log("    flatten:     (only if -flatten)\n");
  75                 log("        proc\n");
  76                 log("        flatten\n");
  77                 log("\n");
  78                 log("    coarse:\n");
  79                 log("        synth -run coarse\n");
  80                 log("        dff2dffe\n");
  81                 log("\n");
  82                 log("    bram:\n");
  83                 log("        memory_bram -rules +/xilinx/brams.txt\n");
  84                 log("        techmap -map +/xilinx/brams_map.v\n");
  85                 log("\n");
  86                 log("    fine:\n");
  87                 log("        opt -fast -full\n");
  88                 log("        memory_map\n");
  89                 log("        opt -full\n");
  90                 log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
  91                 log("        opt -fast\n");
  92                 log("\n");
  93                 log("    map_luts:\n");
  94                 log("        abc -lut 5:8 [-dff]\n");
  95                 log("        clean\n");
  96                 log("\n");
  97                 log("    map_cells:\n");
  98                 log("        techmap -map +/xilinx/cells_map.v\n");
  99                 log("        clean\n");
 100                 log("\n");
 101                 log("    edif:\n");
 102                 log("        write_edif synth.edif\n");
 103                 log("\n");
 104         }
 105         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 106         {
 107                 std::string top_module = "top";
 108                 std::string arch_name = "spartan6";
 109                 std::string edif_file;
 110                 std::string run_from, run_to;
 111                 bool flatten = false;
 112                 bool retime = false;
 113
 114                 size_t argidx;
 115                 for (argidx = 1; argidx < args.size(); argidx++)
 116                 {
 117                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 118                                 top_module = args[++argidx];
 119                                 continue;
 120                         }
 121                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 122                                 edif_file = args[++argidx];
 123                                 continue;
 124                         }
 125                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 126                                 size_t pos = args[argidx+1].find(':');
 127                                 if (pos == std::string::npos)
 128                                         break;
 129                                 run_from = args[++argidx].substr(0, pos);
 130                                 run_to = args[argidx].substr(pos+1);
 131                                 continue;
 132                         }
 133                         if (args[argidx] == "-flatten") {
 134                                 flatten = true;
 135                                 continue;
 136                         }
 137                         if (args[argidx] == "-retime") {
 138                                 retime = true;
 139                                 continue;
 140                         }
 141                         break;
 142                 }
 143                 extra_args(args, argidx, design);
 144
 145                 if (!design->full_selection())
 146                         log_cmd_error("This comannd only operates on fully selected designs!\n");
 147
 148                 bool active = run_from.empty();
 149
 150                 log_header("Executing SYNTH_XILINX pass.\n");
 151                 log_push();
 152
 153                 if (check_label(active, run_from, run_to, "begin"))
 154                 {
 155                         Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
 156                         Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str()));
 157                 }
 158
 159                 if (flatten && check_label(active, run_from, run_to, "flatten"))
 160                 {
 161                         Pass::call(design, "proc");
 162                         Pass::call(design, "flatten");
 163                 }
 164
 165                 if (check_label(active, run_from, run_to, "coarse"))
 166                 {
 167                         Pass::call(design, "synth -run coarse");
 168                         Pass::call(design, "dff2dffe");
 169                 }
 170
 171                 if (check_label(active, run_from, run_to, "bram"))
 172                 {
 173                         Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
 174                         Pass::call(design, "techmap -map +/xilinx/brams_map.v");
 175                 }
 176
 177                 if (check_label(active, run_from, run_to, "fine"))
 178                 {
 179                         Pass::call(design, "opt -fast -full");
 180                         Pass::call(design, "memory_map");
 181                         Pass::call(design, "opt -full");
 182                         Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
 183                         Pass::call(design, "opt -fast");
 184                 }
 185
 186                 if (check_label(active, run_from, run_to, "map_luts"))
 187                 {
 188                         Pass::call(design, "abc -lut 5:8" + string(retime ? " -dff" : ""));
 189                         Pass::call(design, "clean");
 190                 }
 191
 192                 if (check_label(active, run_from, run_to, "map_cells"))
 193                 {
 194                         Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 195                         Pass::call(design, "clean");
 196                 }
 197
 198                 if (check_label(active, run_from, run_to, "edif"))
 199                 {
 200                         if (!edif_file.empty())
 201                                 Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
 202                 }
 203
 204                 log_pop();
 205         }
 206 } SynthXilinxPass;
 207
 208 PRIVATE_NAMESPACE_END