techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 #define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
  29                              // to one LUT6 (instead of a LUT5 + LUT2)
  30
  31 struct SynthXilinxPass : public ScriptPass
  32 {
  33         SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  34
  35         void help() YS_OVERRIDE
  36         {
  37                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  38                 log("\n");
  39                 log("    synth_xilinx [options]\n");
  40                 log("\n");
  41                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  42                 log("partly selected designs. At the moment this command creates netlists that are\n");
  43                 log("compatible with 7-Series Xilinx devices.\n");
  44                 log("\n");
  45                 log("    -top <module>\n");
  46                 log("        use the specified module as top module\n");
  47                 log("\n");
  48                 log("    -family {xcup|xcu|xc7|xc6s}\n");
  49                 log("        run synthesis for the specified Xilinx architecture\n");
  50                 log("        generate the synthesis netlist for the specified family.\n");
  51                 log("        default: xc7\n");
  52                 log("\n");
  53                 log("    -edif <file>\n");
  54                 log("        write the design to the specified edif file. writing of an output file\n");
  55                 log("        is omitted if this parameter is not specified.\n");
  56                 log("\n");
  57                 log("    -blif <file>\n");
  58                 log("        write the design to the specified BLIF file. writing of an output file\n");
  59                 log("        is omitted if this parameter is not specified.\n");
  60                 log("\n");
  61                 log("    -vpr\n");
  62                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  63                 log("        (this feature is experimental and incomplete)\n");
  64                 log("\n");
  65                 log("    -nobram\n");
  66                 log("        disable inference of block rams\n");
  67                 log("\n");
  68                 log("    -nodram\n");
  69                 log("        disable inference of distributed rams\n");
  70                 log("\n");
  71                 log("    -nosrl\n");
  72                 log("        disable inference of shift registers\n");
  73                 log("\n");
  74                 log("    -nocarry\n");
  75                 log("        do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
  76                 log("\n");
  77                 log("    -nowidelut\n");
  78                 log("        do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
  79                 log("\n");
  80                 log("    -run <from_label>:<to_label>\n");
  81                 log("        only run the commands between the labels (see below). an empty\n");
  82                 log("        from label is synonymous to 'begin', and empty to label is\n");
  83                 log("        synonymous to the end of the command list.\n");
  84                 log("\n");
  85                 log("    -flatten\n");
  86                 log("        flatten design before synthesis\n");
  87                 log("\n");
  88                 log("    -retime\n");
  89                 log("        run 'abc' with -dff option\n");
  90                 log("\n");
  91                 log("    -abc9\n");
  92                 log("        use new ABC9 flow (EXPERIMENTAL)\n");
  93                 log("\n");
  94                 log("\n");
  95                 log("The following commands are executed by this synthesis command:\n");
  96                 help_script();
  97                 log("\n");
  98         }
  99
 100         std::string top_opt, edif_file, blif_file, family;
 101         bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
 102
 103         void clear_flags() YS_OVERRIDE
 104         {
 105                 top_opt = "-auto-top";
 106                 edif_file.clear();
 107                 blif_file.clear();
 108                 family = "xc7";
 109                 flatten = false;
 110                 retime = false;
 111                 vpr = false;
 112                 nocarry = false;
 113                 nobram = false;
 114                 nodram = false;
 115                 nosrl = false;
 116                 nocarry = false;
 117                 nowidelut = false;
 118                 abc9 = false;
 119         }
 120
 121         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 122         {
 123                 std::string run_from, run_to;
 124                 clear_flags();
 125
 126                 size_t argidx;
 127                 for (argidx = 1; argidx < args.size(); argidx++)
 128                 {
 129                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 130                                 top_opt = "-top " + args[++argidx];
 131                                 continue;
 132                         }
 133                         if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
 134                                 family = args[++argidx];
 135                                 continue;
 136                         }
 137                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 138                                 edif_file = args[++argidx];
 139                                 continue;
 140                         }
 141                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 142                                 blif_file = args[++argidx];
 143                                 continue;
 144                         }
 145                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 146                                 size_t pos = args[argidx+1].find(':');
 147                                 if (pos == std::string::npos)
 148                                         break;
 149                                 run_from = args[++argidx].substr(0, pos);
 150                                 run_to = args[argidx].substr(pos+1);
 151                                 continue;
 152                         }
 153                         if (args[argidx] == "-flatten") {
 154                                 flatten = true;
 155                                 continue;
 156                         }
 157                         if (args[argidx] == "-retime") {
 158                                 retime = true;
 159                                 continue;
 160                         }
 161                         if (args[argidx] == "-nocarry") {
 162                                 nocarry = true;
 163                                 continue;
 164                         }
 165                         if (args[argidx] == "-nowidelut") {
 166                                 nowidelut = true;
 167                                 continue;
 168                         }
 169                         if (args[argidx] == "-vpr") {
 170                                 vpr = true;
 171                                 continue;
 172                         }
 173                         if (args[argidx] == "-nocarry") {
 174                                 nocarry = true;
 175                                 continue;
 176                         }
 177                         if (args[argidx] == "-nobram") {
 178                                 nobram = true;
 179                                 continue;
 180                         }
 181                         if (args[argidx] == "-nodram") {
 182                                 nodram = true;
 183                                 continue;
 184                         }
 185                         if (args[argidx] == "-nosrl") {
 186                                 nosrl = true;
 187                                 continue;
 188                         }
 189                         if (args[argidx] == "-abc9") {
 190                                 abc9 = true;
 191                                 continue;
 192                         }
 193                         break;
 194                 }
 195                 extra_args(args, argidx, design);
 196
 197                 if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
 198                         log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
 199
 200                 if (!design->full_selection())
 201                         log_cmd_error("This command only operates on fully selected designs!\n");
 202
 203                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 204                 log_push();
 205
 206                 run_script(design, run_from, run_to);
 207
 208                 log_pop();
 209         }
 210
 211         void script() YS_OVERRIDE
 212         {
 213                 if (check_label("begin")) {
 214                         if (vpr)
 215                                 run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 216                         else
 217                                 run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
 218
 219                         run("read_verilog -lib +/xilinx/cells_xtra.v");
 220
 221                         if (!nobram || help_mode)
 222                                 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
 223
 224                         run(stringf("hierarchy -check %s", top_opt.c_str()));
 225                 }
 226
 227                 if (check_label("flatten", "(with '-flatten' only)")) {
 228                         if (flatten || help_mode) {
 229                                 run("proc");
 230                                 run("flatten");
 231                         }
 232                 }
 233
 234                 if (check_label("coarse")) {
 235                         run("synth -run coarse");
 236
 237                         // shregmap -tech xilinx can cope with $shiftx and $mux
 238                         //   cells for identifying variable-length shift registers,
 239                         //   so attempt to convert $pmux-es to the former
 240                         if (!nosrl || help_mode)
 241                                 run("pmux2shiftx", "(skip if '-nosrl')");
 242
 243                         // Run a number of peephole optimisations, including one
 244                         //   that optimises $mul cells driving $shiftx's B input
 245                         //   and that aids wide mux analysis
 246                         run("peepopt");
 247                 }
 248
 249                 if (check_label("bram", "(skip if '-nobram')")) {
 250                         if (!nobram || help_mode) {
 251                                 run("memory_bram -rules +/xilinx/brams.txt");
 252                                 run("techmap -map +/xilinx/brams_map.v");
 253                         }
 254                 }
 255
 256                 if (check_label("dram", "(skip if '-nodram')")) {
 257                         if (!nodram || help_mode) {
 258                                 run("memory_bram -rules +/xilinx/drams.txt");
 259                                 run("techmap -map +/xilinx/drams_map.v");
 260                         }
 261                 }
 262
 263                 if (check_label("fine")) {
 264                         run("opt -fast -full");
 265                         run("memory_map");
 266                         run("dffsr2dff");
 267                         run("dff2dffe");
 268                         run("opt -full");
 269
 270                         if (!nosrl || help_mode) {
 271                                 // shregmap operates on bit-level flops, not word-level,
 272                                 //   so break those down here
 273                                 run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
 274                                 // shregmap with '-tech xilinx' infers variable length shift regs
 275                                 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 276                         }
 277
 278                         std::string techmap_files = " -map +/techmap.v";
 279                         if (help_mode)
 280                                 techmap_files += " [-map +/xilinx/arith_map.v]";
 281                         else if (!nocarry) {
 282                                 techmap_files += " -map +/xilinx/arith_map.v";
 283                                 if (vpr)
 284                                         techmap_files += " -D _EXPLICIT_CARRY";
 285                                 else if (abc9)
 286                                         techmap_files += " -D _CLB_CARRY";
 287                         }
 288                         run("techmap " + techmap_files);
 289                         run("opt -fast");
 290                 }
 291
 292                 if (check_label("map_cells")) {
 293                         run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 294                         run("clean");
 295                 }
 296
 297                 if (check_label("map_luts")) {
 298                         run("opt_expr -mux_undef");
 299                         if (help_mode)
 300                                 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
 301                         else if (abc9) {
 302                                 if (family != "xc7")
 303                                         log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 304                                 if (nowidelut)
 305                                         run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
 306                                 else
 307                                         run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
 308                         }
 309                         else {
 310                                 if (nowidelut)
 311                                         run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 312                                 else
 313                                         run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 314                         }
 315                         run("clean");
 316
 317                         // This shregmap call infers fixed length shift registers after abc
 318                         //   has performed any necessary retiming
 319                         if (!nosrl || help_mode)
 320                                 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 321                         run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 322                         run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 323                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 324                         run("clean");
 325                 }
 326
 327                 if (check_label("check")) {
 328                         run("hierarchy -check");
 329                         run("stat -tech xilinx");
 330                         run("check -noinit");
 331                 }
 332
 333                 if (check_label("edif")) {
 334                         if (!edif_file.empty() || help_mode)
 335                                 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
 336                 }
 337
 338                 if (check_label("blif")) {
 339                         if (!blif_file.empty() || help_mode)
 340                                 run(stringf("write_blif %s", edif_file.c_str()));
 341                 }
 342         }
 343 } SynthXilinxPass;
 344
 345 PRIVATE_NAMESPACE_END