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Merge pull request #1327 from YosysHQ/clifford/pmgen
[yosys.git] / techlibs / xilinx / synth_xilinx.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 #define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
30 // to one LUT6 (instead of a LUT5 + LUT2)
31
32 struct SynthXilinxPass : public ScriptPass
33 {
34 SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
35
36 void help() YS_OVERRIDE
37 {
38 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
39 log("\n");
40 log(" synth_xilinx [options]\n");
41 log("\n");
42 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
43 log("partly selected designs. At the moment this command creates netlists that are\n");
44 log("compatible with 7-Series Xilinx devices.\n");
45 log("\n");
46 log(" -top <module>\n");
47 log(" use the specified module as top module\n");
48 log("\n");
49 log(" -family {xcup|xcu|xc7|xc6s}\n");
50 log(" run synthesis for the specified Xilinx architecture\n");
51 log(" generate the synthesis netlist for the specified family.\n");
52 log(" default: xc7\n");
53 log("\n");
54 log(" -edif <file>\n");
55 log(" write the design to the specified edif file. writing of an output file\n");
56 log(" is omitted if this parameter is not specified.\n");
57 log("\n");
58 log(" -blif <file>\n");
59 log(" write the design to the specified BLIF file. writing of an output file\n");
60 log(" is omitted if this parameter is not specified.\n");
61 log("\n");
62 log(" -vpr\n");
63 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
64 log(" (this feature is experimental and incomplete)\n");
65 log("\n");
66 log(" -nobram\n");
67 log(" do not use block RAM cells in output netlist\n");
68 log("\n");
69 log(" -nolutram\n");
70 log(" do not use distributed RAM cells in output netlist\n");
71 log("\n");
72 log(" -nosrl\n");
73 log(" do not use distributed SRL cells in output netlist\n");
74 log("\n");
75 log(" -nocarry\n");
76 log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
77 log("\n");
78 log(" -nowidelut\n");
79 log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
80 log("\n");
81 log(" -widemux <int>\n");
82 log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
83 log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
84 log(" default: 0 (no inference)\n");
85 log("\n");
86 log(" -run <from_label>:<to_label>\n");
87 log(" only run the commands between the labels (see below). an empty\n");
88 log(" from label is synonymous to 'begin', and empty to label is\n");
89 log(" synonymous to the end of the command list.\n");
90 log("\n");
91 log(" -flatten\n");
92 log(" flatten design before synthesis\n");
93 log("\n");
94 log(" -retime\n");
95 log(" run 'abc' with -dff option\n");
96 log("\n");
97 log(" -abc9\n");
98 log(" use new ABC9 flow (EXPERIMENTAL)\n");
99 log("\n");
100 log("\n");
101 log("The following commands are executed by this synthesis command:\n");
102 help_script();
103 log("\n");
104 }
105
106 std::string top_opt, edif_file, blif_file, family;
107 bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
108 bool flatten_before_abc;
109 int widemux;
110
111 void clear_flags() YS_OVERRIDE
112 {
113 top_opt = "-auto-top";
114 edif_file.clear();
115 blif_file.clear();
116 family = "xc7";
117 flatten = false;
118 retime = false;
119 vpr = false;
120 nocarry = false;
121 nobram = false;
122 nolutram = false;
123 nosrl = false;
124 nocarry = false;
125 nowidelut = false;
126 abc9 = false;
127 flatten_before_abc = false;
128 widemux = 0;
129 }
130
131 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
132 {
133 std::string run_from, run_to;
134 clear_flags();
135
136 size_t argidx;
137 for (argidx = 1; argidx < args.size(); argidx++)
138 {
139 if (args[argidx] == "-top" && argidx+1 < args.size()) {
140 top_opt = "-top " + args[++argidx];
141 continue;
142 }
143 if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
144 family = args[++argidx];
145 continue;
146 }
147 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
148 edif_file = args[++argidx];
149 continue;
150 }
151 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
152 blif_file = args[++argidx];
153 continue;
154 }
155 if (args[argidx] == "-run" && argidx+1 < args.size()) {
156 size_t pos = args[argidx+1].find(':');
157 if (pos == std::string::npos)
158 break;
159 run_from = args[++argidx].substr(0, pos);
160 run_to = args[argidx].substr(pos+1);
161 continue;
162 }
163 if (args[argidx] == "-flatten") {
164 flatten = true;
165 continue;
166 }
167 if (args[argidx] == "-flatten_before_abc") {
168 flatten_before_abc = true;
169 continue;
170 }
171 if (args[argidx] == "-retime") {
172 retime = true;
173 continue;
174 }
175 if (args[argidx] == "-nocarry") {
176 nocarry = true;
177 continue;
178 }
179 if (args[argidx] == "-nowidelut") {
180 nowidelut = true;
181 continue;
182 }
183 if (args[argidx] == "-vpr") {
184 vpr = true;
185 continue;
186 }
187 if (args[argidx] == "-nocarry") {
188 nocarry = true;
189 continue;
190 }
191 if (args[argidx] == "-nobram") {
192 nobram = true;
193 continue;
194 }
195 if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
196 nolutram = true;
197 continue;
198 }
199 if (args[argidx] == "-nosrl") {
200 nosrl = true;
201 continue;
202 }
203 if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
204 widemux = atoi(args[++argidx].c_str());
205 continue;
206 }
207 if (args[argidx] == "-abc9") {
208 abc9 = true;
209 continue;
210 }
211 break;
212 }
213 extra_args(args, argidx, design);
214
215 if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
216 log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
217
218 if (widemux != 0 && widemux < 2)
219 log_cmd_error("-widemux value must be 0 or >= 2.\n");
220
221 if (!design->full_selection())
222 log_cmd_error("This command only operates on fully selected designs!\n");
223
224 if (abc9 && retime)
225 log_cmd_error("-retime option not currently compatible with -abc9!\n");
226
227 log_header(design, "Executing SYNTH_XILINX pass.\n");
228 log_push();
229
230 run_script(design, run_from, run_to);
231
232 log_pop();
233 }
234
235 void script() YS_OVERRIDE
236 {
237 if (check_label("begin")) {
238 if (vpr)
239 run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
240 else
241 run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
242
243 run("read_verilog -lib +/xilinx/cells_xtra.v");
244
245 if (help_mode) {
246 run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
247 } else if (family == "xc6s") {
248 run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
249 } else if (family == "xc7") {
250 run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
251 }
252
253 run(stringf("hierarchy -check %s", top_opt.c_str()));
254 }
255
256 if (check_label("coarse")) {
257 run("proc");
258 if (help_mode || flatten)
259 run("flatten", "(if -flatten)");
260 run("opt_expr");
261 run("opt_clean");
262 run("check");
263 run("opt");
264 if (help_mode)
265 run("wreduce [-keepdc]", "(option for '-widemux')");
266 else
267 run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
268 run("peepopt");
269 run("opt_clean");
270
271 if (widemux > 0 || help_mode)
272 run("muxpack", " ('-widemux' only)");
273
274 // shregmap -tech xilinx can cope with $shiftx and $mux
275 // cells for identifying variable-length shift registers,
276 // so attempt to convert $pmux-es to the former
277 // Also: wide multiplexer inference benefits from this too
278 if (!(nosrl && widemux == 0) || help_mode) {
279 run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
280 run("clean", " (skip if '-nosrl' and '-widemux=0')");
281 }
282
283 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
284 run("alumacc");
285 run("share");
286 run("opt");
287 run("fsm");
288 run("opt -fast");
289 run("memory -nomap");
290 run("opt_clean");
291 }
292
293 if (check_label("map_bram", "(skip if '-nobram')")) {
294 if (help_mode) {
295 run("memory_bram -rules +/xilinx/{family}_brams.txt");
296 run("techmap -map +/xilinx/{family}_brams_map.v");
297 } else if (!nobram) {
298 if (family == "xc6s") {
299 run("memory_bram -rules +/xilinx/xc6s_brams.txt");
300 run("techmap -map +/xilinx/xc6s_brams_map.v");
301 } else if (family == "xc7") {
302 run("memory_bram -rules +/xilinx/xc7_brams.txt");
303 run("techmap -map +/xilinx/xc7_brams_map.v");
304 } else {
305 log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
306 }
307 }
308 }
309
310 if (check_label("map_lutram", "(skip if '-nolutram')")) {
311 if (!nolutram || help_mode) {
312 run("memory_bram -rules +/xilinx/lutrams.txt");
313 run("techmap -map +/xilinx/lutrams_map.v");
314 }
315 }
316
317 if (check_label("map_ffram")) {
318 if (widemux > 0)
319 run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
320 // performs less efficiently
321 else
322 run("opt -fast -full");
323 run("memory_map");
324 }
325
326 if (check_label("fine")) {
327 run("dffsr2dff");
328 run("dff2dffe");
329 if (help_mode) {
330 run("simplemap t:$mux", " ('-widemux' only)");
331 run("muxcover <internal options>, ('-widemux' only)");
332 }
333 else if (widemux > 0) {
334 run("simplemap t:$mux");
335 constexpr int cost_mux2 = 100;
336 std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
337 switch (widemux) {
338 case 2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
339 case 3:
340 case 4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
341 case 5:
342 case 6:
343 case 7:
344 case 8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
345 case 9:
346 case 10:
347 case 11:
348 case 12:
349 case 13:
350 case 14:
351 case 15:
352 default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break;
353 }
354 run("muxcover " + muxcover_args);
355 }
356 run("opt -full");
357
358 if (!nosrl || help_mode) {
359 // shregmap operates on bit-level flops, not word-level,
360 // so break those down here
361 run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
362 // shregmap with '-tech xilinx' infers variable length shift regs
363 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
364 }
365
366 std::string techmap_args = " -map +/techmap.v";
367 if (help_mode)
368 techmap_args += " [-map +/xilinx/mux_map.v]";
369 else if (widemux > 0)
370 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
371 if (help_mode)
372 techmap_args += " [-map +/xilinx/arith_map.v]";
373 else if (!nocarry) {
374 techmap_args += " -map +/xilinx/arith_map.v";
375 if (vpr)
376 techmap_args += " -D _EXPLICIT_CARRY";
377 else if (abc9)
378 techmap_args += " -D _CLB_CARRY";
379 }
380 run("techmap " + techmap_args);
381 run("opt -fast");
382 }
383
384 if (check_label("map_cells")) {
385 std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
386 if (widemux > 0)
387 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
388 run("techmap " + techmap_args);
389 run("clean");
390 }
391
392 if (check_label("map_luts")) {
393 run("opt_expr -mux_undef");
394 if (flatten_before_abc)
395 run("flatten");
396 if (help_mode)
397 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
398 else if (abc9) {
399 if (family != "xc7")
400 log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
401 if (nowidelut)
402 run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
403 else
404 run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
405 }
406 else {
407 if (nowidelut)
408 run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
409 else
410 run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
411 }
412 run("clean");
413
414 // This shregmap call infers fixed length shift registers after abc
415 // has performed any necessary retiming
416 if (!nosrl || help_mode)
417 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
418 run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
419 run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
420 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
421 run("clean");
422 }
423
424 if (check_label("check")) {
425 run("hierarchy -check");
426 run("stat -tech xilinx");
427 run("check -noinit");
428 }
429
430 if (check_label("edif")) {
431 if (!edif_file.empty() || help_mode)
432 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
433 }
434
435 if (check_label("blif")) {
436 if (!blif_file.empty() || help_mode)
437 run(stringf("write_blif %s", edif_file.c_str()));
438 }
439 }
440 } SynthXilinxPass;
441
442 PRIVATE_NAMESPACE_END