2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 #define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
29 // to one LUT6 (instead of a LUT5 + LUT2)
31 struct SynthXilinxPass
: public ScriptPass
33 SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
35 void help() YS_OVERRIDE
37 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
39 log(" synth_xilinx [options]\n");
41 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
42 log("partly selected designs. At the moment this command creates netlists that are\n");
43 log("compatible with 7-Series Xilinx devices.\n");
45 log(" -top <module>\n");
46 log(" use the specified module as top module\n");
48 log(" -arch {xcup|xcu|xc7|xc6s}\n");
49 log(" run synthesis for the specified Xilinx architecture\n");
50 log(" default: xc7\n");
52 log(" -edif <file>\n");
53 log(" write the design to the specified edif file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
56 log(" -blif <file>\n");
57 log(" write the design to the specified BLIF file. writing of an output file\n");
58 log(" is omitted if this parameter is not specified.\n");
61 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
62 log(" (this feature is experimental and incomplete)\n");
65 log(" disable inference of carry chains\n");
68 log(" disable inference of block rams\n");
71 log(" disable inference of distributed rams\n");
74 log(" disable inference of shift registers\n");
77 log(" disable inference of wide multiplexers\n");
79 log(" -run <from_label>:<to_label>\n");
80 log(" only run the commands between the labels (see below). an empty\n");
81 log(" from label is synonymous to 'begin', and empty to label is\n");
82 log(" synonymous to the end of the command list.\n");
85 log(" flatten design before synthesis\n");
88 log(" run 'abc' with -dff option\n");
91 log(" use new ABC9 flow (EXPERIMENTAL)\n");
94 log("The following commands are executed by this synthesis command:\n");
99 std::string top_opt
, edif_file
, blif_file
, abc
, arch
;
100 bool flatten
, retime
, vpr
, nocarry
, nobram
, nodram
, nosrl
, nomux
;
102 void clear_flags() YS_OVERRIDE
104 top_opt
= "-auto-top";
119 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
121 std::string run_from
, run_to
;
125 for (argidx
= 1; argidx
< args
.size(); argidx
++)
127 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
128 top_opt
= "-top " + args
[++argidx
];
131 if (args
[argidx
] == "-arch" && argidx
+1 < args
.size()) {
132 arch
= args
[++argidx
];
135 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
136 edif_file
= args
[++argidx
];
139 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
140 blif_file
= args
[++argidx
];
143 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
144 size_t pos
= args
[argidx
+1].find(':');
145 if (pos
== std::string::npos
)
147 run_from
= args
[++argidx
].substr(0, pos
);
148 run_to
= args
[argidx
].substr(pos
+1);
151 if (args
[argidx
] == "-flatten") {
155 if (args
[argidx
] == "-retime") {
159 if (args
[argidx
] == "-vpr") {
163 if (args
[argidx
] == "-nocarry") {
167 if (args
[argidx
] == "-nobram") {
171 if (args
[argidx
] == "-nodram") {
175 if (args
[argidx
] == "-nosrl") {
179 if (args
[argidx
] == "-nomux") {
183 if (args
[argidx
] == "-abc9") {
189 extra_args(args
, argidx
, design
);
191 if (arch
!= "xcup" && arch
!= "xcu" && arch
!= "xc7" && arch
!= "xc6s")
192 log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch
.c_str());
194 if (!design
->full_selection())
195 log_cmd_error("This command only operates on fully selected designs!\n");
197 log_header(design
, "Executing SYNTH_XILINX pass.\n");
200 run_script(design
, run_from
, run_to
);
205 void script() YS_OVERRIDE
207 if (check_label("begin")) {
209 run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
211 run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
213 run("read_verilog -lib +/xilinx/cells_xtra.v");
215 if (!nobram
|| help_mode
)
216 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
218 run(stringf("hierarchy -check %s", top_opt
.c_str()));
221 if (check_label("coarse")) {
223 if (flatten
|| help_mode
)
224 run("flatten", "(with -flatten only)");
230 run("wreduce [c:* t:$mux %d]", "(no selection if -nomux)");
232 run("wreduce" + nomux
? "" : " c:* t:$mux %d");
240 run("memory -nomap");
243 if (!nomux
|| help_mode
)
244 run("muxpack", " (skip if '-nomux')");
246 // shregmap -tech xilinx can cope with $shiftx and $mux
247 // cells for identifying variable-length shift registers,
248 // so attempt to convert $pmux-es to the former
249 // Also: wide multiplexer inference benefits from this too
250 if (!(nosrl
&& nomux
) || help_mode
)
251 run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
254 if (check_label("bram", "(skip if '-nobram')")) {
255 if (!nobram
|| help_mode
) {
256 run("memory_bram -rules +/xilinx/brams.txt");
257 run("techmap -map +/xilinx/brams_map.v");
261 if (check_label("dram", "(skip if '-nodram')")) {
262 if (!nodram
|| help_mode
) {
263 run("memory_bram -rules +/xilinx/drams.txt");
264 run("techmap -map +/xilinx/drams_map.v");
268 if (check_label("fine")) {
273 if (!nomux
|| help_mode
) {
274 run("simplemap t:$mux", " (skip if -nomux)");
275 // FIXME: Must specify mux4, even if we don't need it,
276 // otherwise it will use mux8 as mux4
277 run("muxcover -mux4=150 -mux8=200 -mux16=250 -dmux=0", "(skip if -nomux)");
281 if (!nosrl
|| help_mode
) {
282 // shregmap operates on bit-level flops, not word-level,
283 // so break those down here
284 run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
285 // shregmap with '-tech xilinx' infers variable length shift regs
286 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
289 std::string techmap_files
= " -map +/techmap.v";
291 techmap_files
+= " [-map +/xilinx/mux_map.v]";
293 techmap_files
+= " -map +/xilinx/mux_map.v";
295 techmap_files
+= " [-map +/xilinx/arith_map.v]";
297 techmap_files
+= " -map +/xilinx/arith_map.v";
299 techmap_files
+= " -D _EXPLICIT_CARRY";
300 else if (abc
== "abc9")
301 techmap_files
+= " -D _CLB_CARRY";
303 run("techmap " + techmap_files
);
307 if (check_label("map_cells")) {
308 run("techmap -map +/techmap.v -D _ABC -map +/xilinx/cells_map.v");
312 if (check_label("map_luts")) {
313 run("opt_expr -mux_undef");
315 run(abc
+ " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY
+ string(retime
? " -dff" : ""));
317 run(abc
+ " -luts 2:2,3,6:5,10,20 [-dff]");
319 run(abc
+ " -luts 2:2,3,6:5,10,20" + string(retime
? " -dff" : ""));
322 // This shregmap call infers fixed length shift registers after abc
323 // has performed any necessary retiming
324 if (!nosrl
|| help_mode
)
325 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
326 run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
327 run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
328 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
332 if (check_label("check")) {
333 run("hierarchy -check");
334 run("stat -tech xilinx");
335 run("check -noinit");
338 if (check_label("edif")) {
339 if (!edif_file
.empty() || help_mode
)
340 run(stringf("write_edif -pvector bra %s", edif_file
.c_str()));
343 if (check_label("blif")) {
344 if (!blif_file
.empty() || help_mode
)
345 run(stringf("write_blif %s", edif_file
.c_str()));
350 PRIVATE_NAMESPACE_END