techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
  29 {
  30         if (label == run_from)
  31                 active = true;
  32         if (label == run_to)
  33                 active = false;
  34         return active;
  35 }
  36
  37 struct SynthXilinxPass : public Pass
  38 {
  39         SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  40
  41         void help() YS_OVERRIDE
  42         {
  43                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  44                 log("\n");
  45                 log("    synth_xilinx [options]\n");
  46                 log("\n");
  47                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  48                 log("partly selected designs. At the moment this command creates netlists that are\n");
  49                 log("compatible with 7-Series Xilinx devices.\n");
  50                 log("\n");
  51                 log("    -top <module>\n");
  52                 log("        use the specified module as top module\n");
  53                 log("\n");
  54                 log("    -edif <file>\n");
  55                 log("        write the design to the specified edif file. writing of an output file\n");
  56                 log("        is omitted if this parameter is not specified.\n");
  57                 log("\n");
  58                 log("    -blif <file>\n");
  59                 log("        write the design to the specified BLIF file. writing of an output file\n");
  60                 log("        is omitted if this parameter is not specified.\n");
  61                 log("\n");
  62                 log("    -vpr\n");
  63                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  64                 log("        (this feature is experimental and incomplete)\n");
  65                 log("\n");
  66                 log("    -nobram\n");
  67                 log("        disable infering of block rams\n");
  68                 log("\n");
  69                 log("    -nodram\n");
  70                 log("        disable infering of distributed rams\n");
  71                 log("\n");
  72                 log("    -run <from_label>:<to_label>\n");
  73                 log("        only run the commands between the labels (see below). an empty\n");
  74                 log("        from label is synonymous to 'begin', and empty to label is\n");
  75                 log("        synonymous to the end of the command list.\n");
  76                 log("\n");
  77                 log("    -flatten\n");
  78                 log("        flatten design before synthesis\n");
  79                 log("\n");
  80                 log("    -retime\n");
  81                 log("        run 'abc' with -dff option\n");
  82                 log("\n");
  83                 log("\n");
  84                 log("The following commands are executed by this synthesis command:\n");
  85                 log("\n");
  86                 log("    begin:\n");
  87                 log("        read_verilog -lib +/xilinx/cells_sim.v\n");
  88                 log("        read_verilog -lib +/xilinx/cells_xtra.v\n");
  89                 log("        read_verilog -lib +/xilinx/brams_bb.v\n");
  90                 log("        hierarchy -check -top <top>\n");
  91                 log("\n");
  92                 log("    flatten:     (only if -flatten)\n");
  93                 log("        proc\n");
  94                 log("        flatten\n");
  95                 log("\n");
  96                 log("    coarse:\n");
  97                 log("        synth -run coarse\n");
  98                 log("\n");
  99                 log("    bram: (only executed when '-nobram' is not given)\n");
 100                 log("        memory_bram -rules +/xilinx/brams.txt\n");
 101                 log("        techmap -map +/xilinx/brams_map.v\n");
 102                 log("\n");
 103                 log("    dram: (only executed when '-nodram' is not given)\n");
 104                 log("        memory_bram -rules +/xilinx/drams.txt\n");
 105                 log("        techmap -map +/xilinx/drams_map.v\n");
 106                 log("\n");
 107                 log("    fine:\n");
 108                 log("        opt -fast -full\n");
 109                 log("        memory_map\n");
 110                 log("        dffsr2dff\n");
 111                 log("        dff2dffe\n");
 112                 log("        opt -full\n");
 113                 log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
 114                 log("        opt -fast\n");
 115                 log("\n");
 116                 log("    map_luts:\n");
 117                 log("        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
 118                 log("        abc -lut 5 [-dff] (with '-vpr' only!)\n");
 119                 log("        clean\n");
 120                 log("\n");
 121                 log("    map_cells:\n");
 122                 log("        techmap -map +/xilinx/cells_map.v\n");
 123                 log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
 124                 log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
 125                 log("        clean\n");
 126                 log("\n");
 127                 log("    check:\n");
 128                 log("        hierarchy -check\n");
 129                 log("        stat\n");
 130                 log("        check -noinit\n");
 131                 log("\n");
 132                 log("    edif:     (only if -edif)\n");
 133                 log("        write_edif <file-name>\n");
 134                 log("\n");
 135                 log("    blif:     (only if -blif)\n");
 136                 log("        write_blif <file-name>\n");
 137                 log("\n");
 138         }
 139         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 140         {
 141                 std::string top_opt = "-auto-top";
 142                 std::string edif_file;
 143                 std::string blif_file;
 144                 std::string run_from, run_to;
 145                 bool flatten = false;
 146                 bool retime = false;
 147                 bool vpr = false;
 148                 bool nobram = false;
 149                 bool nodram = false;
 150
 151                 size_t argidx;
 152                 for (argidx = 1; argidx < args.size(); argidx++)
 153                 {
 154                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 155                                 top_opt = "-top " + args[++argidx];
 156                                 continue;
 157                         }
 158                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 159                                 edif_file = args[++argidx];
 160                                 continue;
 161                         }
 162                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 163                                 blif_file = args[++argidx];
 164                                 continue;
 165                         }
 166                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 167                                 size_t pos = args[argidx+1].find(':');
 168                                 if (pos == std::string::npos)
 169                                         break;
 170                                 run_from = args[++argidx].substr(0, pos);
 171                                 run_to = args[argidx].substr(pos+1);
 172                                 continue;
 173                         }
 174                         if (args[argidx] == "-flatten") {
 175                                 flatten = true;
 176                                 continue;
 177                         }
 178                         if (args[argidx] == "-retime") {
 179                                 retime = true;
 180                                 continue;
 181                         }
 182                         if (args[argidx] == "-vpr") {
 183                                 vpr = true;
 184                                 continue;
 185                         }
 186                         if (args[argidx] == "-nobram") {
 187                                 nobram = true;
 188                                 continue;
 189                         }
 190                         if (args[argidx] == "-nodram") {
 191                                 nodram = true;
 192                                 continue;
 193                         }
 194                         break;
 195                 }
 196                 extra_args(args, argidx, design);
 197
 198                 if (!design->full_selection())
 199                         log_cmd_error("This command only operates on fully selected designs!\n");
 200
 201                 bool active = run_from.empty();
 202
 203                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 204                 log_push();
 205
 206                 if (check_label(active, run_from, run_to, "begin"))
 207                 {
 208                         if (vpr) {
 209                                 Pass::call(design, "read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 210                         } else {
 211                                 Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
 212                         }
 213
 214                         Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
 215
 216                         if (!nobram) {
 217                                 Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
 218                         }
 219
 220                         Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
 221                 }
 222
 223                 if (flatten && check_label(active, run_from, run_to, "flatten"))
 224                 {
 225                         Pass::call(design, "proc");
 226                         Pass::call(design, "flatten");
 227                 }
 228
 229                 if (check_label(active, run_from, run_to, "coarse"))
 230                 {
 231                         Pass::call(design, "synth -run coarse");
 232                 }
 233
 234                 if (check_label(active, run_from, run_to, "bram"))
 235                 {
 236                         if (!nobram) {
 237                                 Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
 238                                 Pass::call(design, "techmap -map +/xilinx/brams_map.v");
 239                         }
 240                 }
 241
 242                 if (check_label(active, run_from, run_to, "dram"))
 243                 {
 244                         if (!nodram) {
 245                                 Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
 246                                 Pass::call(design, "techmap -map +/xilinx/drams_map.v");
 247                         }
 248                 }
 249
 250                 if (check_label(active, run_from, run_to, "fine"))
 251                 {
 252                         Pass::call(design, "opt -fast -full");
 253                         Pass::call(design, "memory_map");
 254                         Pass::call(design, "dffsr2dff");
 255                         Pass::call(design, "dff2dffe");
 256                         Pass::call(design, "opt -full");
 257
 258                         if (vpr) {
 259                                 Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
 260                         } else {
 261                                 Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
 262                         }
 263
 264                         Pass::call(design, "hierarchy -check");
 265                         Pass::call(design, "opt -fast");
 266                 }
 267
 268                 if (check_label(active, run_from, run_to, "map_luts"))
 269                 {
 270                         Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 271                         Pass::call(design, "clean");
 272                         Pass::call(design, "techmap -map +/xilinx/lut_map.v");
 273                 }
 274
 275                 if (check_label(active, run_from, run_to, "map_cells"))
 276                 {
 277                         Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 278                         Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 279                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 280                         Pass::call(design, "clean");
 281                 }
 282
 283                 if (check_label(active, run_from, run_to, "check"))
 284                 {
 285                         Pass::call(design, "hierarchy -check");
 286                         Pass::call(design, "stat");
 287                         Pass::call(design, "check -noinit");
 288                 }
 289
 290                 if (check_label(active, run_from, run_to, "edif"))
 291                 {
 292                         if (!edif_file.empty())
 293                                 Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str()));
 294                 }
 295                 if (check_label(active, run_from, run_to, "blif"))
 296                 {
 297                         if (!blif_file.empty())
 298                                 Pass::call(design, stringf("write_blif %s", edif_file.c_str()));
 299                 }
 300
 301                 log_pop();
 302         }
 303 } SynthXilinxPass;
 304
 305 PRIVATE_NAMESPACE_END