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Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
[yosys.git] / techlibs / xilinx / tests / test_dsp_model.v
1 `timescale 1ns / 1ps
2
3 module testbench;
4 parameter integer ACASCREG = 1;
5 parameter integer ADREG = 1;
6 parameter integer ALUMODEREG = 1;
7 parameter integer AREG = 1;
8 parameter AUTORESET_PATDET = "NO_RESET";
9 parameter A_INPUT = "DIRECT";
10 parameter integer BCASCREG = 1;
11 parameter integer BREG = 1;
12 parameter B_INPUT = "DIRECT";
13 parameter integer CARRYINREG = 1;
14 parameter integer CARRYINSELREG = 1;
15 parameter integer CREG = 1;
16 parameter integer DREG = 1;
17 parameter integer INMODEREG = 1;
18 parameter integer MREG = 1;
19 parameter integer OPMODEREG = 1;
20 parameter integer PREG = 1;
21 parameter SEL_MASK = "MASK";
22 parameter SEL_PATTERN = "PATTERN";
23 parameter USE_DPORT = "FALSE";
24 parameter USE_MULT = "MULTIPLY";
25 parameter USE_PATTERN_DETECT = "NO_PATDET";
26 parameter USE_SIMD = "ONE48";
27 parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
28 parameter [47:0] PATTERN = 48'h000000000000;
29 parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
30 parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
31 parameter [0:0] IS_CLK_INVERTED = 1'b0;
32 parameter [4:0] IS_INMODE_INVERTED = 5'b0;
33 parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
34
35 reg CLK;
36 reg CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL;
37 reg CED, CEINMODE, CEM, CEP;
38 reg RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP;
39 reg [29:0] A, ACIN;
40 reg [17:0] B, BCIN;
41 reg [47:0] C;
42 reg [24:0] D;
43 reg [47:0] PCIN;
44 reg [3:0] ALUMODE;
45 reg [2:0] CARRYINSEL;
46 reg [4:0] INMODE;
47 reg [6:0] OPMODE;
48 reg CARRYCASCIN, CARRYIN, MULTSIGNIN;
49
50 output [29:0] ACOUT, REF_ACOUT;
51 output [17:0] BCOUT, REF_BCOUT;
52 output CARRYCASCOUT, REF_CARRYCASCOUT;
53 output [3:0] CARRYOUT, REF_CARRYOUT;
54 output MULTSIGNOUT, REF_MULTSIGNOUT;
55 output OVERFLOW, REF_OVERFLOW;
56 output [47:0] P, REF_P;
57 output PATTERNBDETECT, REF_PATTERNBDETECT;
58 output PATTERNDETECT, REF_PATTERNDETECT;
59 output [47:0] PCOUT, REF_PCOUT;
60 output UNDERFLOW, REF_UNDERFLOW;
61
62 integer errcount = 0;
63
64 reg ERROR_FLAG = 0;
65
66 task clkcycle;
67 begin
68 #5;
69 CLK = ~CLK;
70 #10;
71 CLK = ~CLK;
72 #2;
73 ERROR_FLAG = 0;
74 if (REF_P !== P) begin
75 $display("ERROR at %1t: REF_P=%b UUT_P=%b DIFF=%b", $time, REF_P, P, REF_P ^ P);
76 errcount = errcount + 1;
77 ERROR_FLAG = 1;
78 end
79 if (REF_CARRYOUT !== CARRYOUT) begin
80 $display("ERROR at %1t: REF_CARRYOUT=%b UUT_CARRYOUT=%b", $time, REF_CARRYOUT, CARRYOUT);
81 errcount = errcount + 1;
82 ERROR_FLAG = 1;
83 end
84 if (REF_PATTERNDETECT !== PATTERNDETECT) begin
85 $display("ERROR at %1t: REF_PATTERNDETECT=%b UUT_PATTERNDETECT=%b DIFF=%b REF_P=%b P=%b", $time, REF_PATTERNDETECT, PATTERNDETECT, REF_PATTERNDETECT ^ PATTERNDETECT, REF_P, P);
86 errcount = errcount + 1;
87 ERROR_FLAG = 1;
88 end
89 if (REF_PATTERNBDETECT !== PATTERNBDETECT) begin
90 $display("ERROR at %1t: REF_PATTERNBDETECT=%b UUT_PATTERNBDETECT=%b DIFF=%b", $time, REF_PATTERNBDETECT, PATTERNBDETECT, REF_PATTERNBDETECT ^ PATTERNBDETECT);
91 errcount = errcount + 1;
92 ERROR_FLAG = 1;
93 end
94 if (REF_OVERFLOW !== OVERFLOW) begin
95 $display("ERROR at %1t: REF_OVERFLOW=%b UUT_OVERFLOW=%b DIFF=%b", $time, REF_OVERFLOW, OVERFLOW, REF_OVERFLOW ^ OVERFLOW);
96 errcount = errcount + 1;
97 ERROR_FLAG = 1;
98 end
99 if (REF_UNDERFLOW !== UNDERFLOW) begin
100 $display("ERROR at %1t: REF_UNDERFLOW=%b UUT_UNDERFLOW=%b DIFF=%b", $time, REF_UNDERFLOW, UNDERFLOW, REF_UNDERFLOW ^ UNDERFLOW);
101 errcount = errcount + 1;
102 ERROR_FLAG = 1;
103 end
104 #3;
105 end
106 endtask
107
108 reg config_valid = 0;
109 task drc;
110 begin
111 config_valid = 1;
112 if (AREG != 2 && INMODE[0]) config_valid = 0;
113 if (BREG != 2 && INMODE[4]) config_valid = 0;
114
115 if (USE_SIMD != "ONE48" && OPMODE[3:0] == 4'b0101) config_valid = 0;
116
117 if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0;
118 if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
119 if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0;
120 if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000 || ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11)) config_valid = 0;
121 if ((CARRYINSEL == 3'b100 || CARRYINSEL == 3'b101 || CARRYINSEL == 3'b111) && (PREG != 1)) config_valid = 0;
122 if (OPMODE[6:4] == 3'b111) config_valid = 0;
123 if ((OPMODE[3:0] == 4'b0101) && CARRYINSEL == 3'b010) config_valid = 0;
124 if (CARRYINSEL == 3'b000 && OPMODE == 7'b1001000) config_valid = 0;
125
126 if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0;
127
128
129 end
130 endtask
131
132 initial begin
133 $dumpfile("test_dsp_model.vcd");
134 $dumpvars(0, testbench);
135
136 #2;
137 CLK = 1'b0;
138 {CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = 9'b111111111;
139 {CED, CEINMODE, CEM, CEP} = 4'b1111;
140
141 {A, B, C, D} = 0;
142 {ACIN, BCIN, PCIN} = 0;
143 {ALUMODE, CARRYINSEL, INMODE} = 0;
144 {OPMODE, CARRYCASCIN, CARRYIN, MULTSIGNIN} = 0;
145
146 {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = ~0;
147 repeat (10) begin
148 #10;
149 CLK = 1'b1;
150 #10;
151 CLK = 1'b0;
152 #10;
153 CLK = 1'b1;
154 #10;
155 CLK = 1'b0;
156 end
157 {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0;
158
159 repeat (10000) begin
160 clkcycle;
161 config_valid = 0;
162 while (!config_valid) begin
163 A = $urandom;
164 ACIN = $urandom;
165 B = $urandom;
166 BCIN = $urandom;
167 C = {$urandom, $urandom};
168 D = $urandom;
169 PCIN = {$urandom, $urandom};
170
171 {CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = $urandom | $urandom | $urandom;
172 {CED, CEINMODE, CEM, CEP} = $urandom | $urandom | $urandom | $urandom;
173
174 // Otherwise we can accidentally create illegal configs
175 CEINMODE = CECTRL;
176 CEALUMODE = CECTRL;
177
178 {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
179 {ALUMODE, INMODE} = $urandom;
180 CARRYINSEL = $urandom & $urandom & $urandom;
181 OPMODE = $urandom;
182 if ($urandom & 1'b1)
183 OPMODE[3:0] = 4'b0101; // test multiply more than other modes
184 {CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom;
185
186 // So few valid options in these modes, just force one valid option
187 if (CARRYINSEL == 3'b001) OPMODE = 7'b1010101;
188 if (CARRYINSEL == 3'b010) OPMODE = 7'b0001010;
189 if (CARRYINSEL == 3'b011) OPMODE = 7'b0011011;
190 if (CARRYINSEL == 3'b100) OPMODE = 7'b0110011;
191 if (CARRYINSEL == 3'b101) OPMODE = 7'b0011010;
192 if (CARRYINSEL == 3'b110) OPMODE = 7'b0010101;
193 if (CARRYINSEL == 3'b111) OPMODE = 7'b0100011;
194
195 drc;
196 end
197 end
198
199 if (errcount == 0) begin
200 $display("All tests passed.");
201 $finish;
202 end else begin
203 $display("Caught %1d errors.", errcount);
204 $stop;
205 end
206 end
207
208 DSP48E1 #(
209 .ACASCREG (ACASCREG),
210 .ADREG (ADREG),
211 .ALUMODEREG (ALUMODEREG),
212 .AREG (AREG),
213 .AUTORESET_PATDET (AUTORESET_PATDET),
214 .A_INPUT (A_INPUT),
215 .BCASCREG (BCASCREG),
216 .BREG (BREG),
217 .B_INPUT (B_INPUT),
218 .CARRYINREG (CARRYINREG),
219 .CARRYINSELREG (CARRYINSELREG),
220 .CREG (CREG),
221 .DREG (DREG),
222 .INMODEREG (INMODEREG),
223 .MREG (MREG),
224 .OPMODEREG (OPMODEREG),
225 .PREG (PREG),
226 .SEL_MASK (SEL_MASK),
227 .SEL_PATTERN (SEL_PATTERN),
228 .USE_DPORT (USE_DPORT),
229 .USE_MULT (USE_MULT),
230 .USE_PATTERN_DETECT (USE_PATTERN_DETECT),
231 .USE_SIMD (USE_SIMD),
232 .MASK (MASK),
233 .PATTERN (PATTERN),
234 .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
235 .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
236 .IS_CLK_INVERTED (IS_CLK_INVERTED),
237 .IS_INMODE_INVERTED (IS_INMODE_INVERTED),
238 .IS_OPMODE_INVERTED (IS_OPMODE_INVERTED)
239 ) ref (
240 .ACOUT (REF_ACOUT),
241 .BCOUT (REF_BCOUT),
242 .CARRYCASCOUT (REF_CARRYCASCOUT),
243 .CARRYOUT (REF_CARRYOUT),
244 .MULTSIGNOUT (REF_MULTSIGNOUT),
245 .OVERFLOW (REF_OVERFLOW),
246 .P (REF_P),
247 .PATTERNBDETECT(REF_PATTERNBDETECT),
248 .PATTERNDETECT (REF_PATTERNDETECT),
249 .PCOUT (REF_PCOUT),
250 .UNDERFLOW (REF_UNDERFLOW),
251 .A (A),
252 .ACIN (ACIN),
253 .ALUMODE (ALUMODE),
254 .B (B),
255 .BCIN (BCIN),
256 .C (C),
257 .CARRYCASCIN (CARRYCASCIN),
258 .CARRYINSEL (CARRYINSEL),
259 .CEA1 (CEA1),
260 .CEA2 (CEA2),
261 .CEAD (CEAD),
262 .CEALUMODE (CEALUMODE),
263 .CEB1 (CEB1),
264 .CEB2 (CEB2),
265 .CEC (CEC),
266 .CECARRYIN (CECARRYIN),
267 .CECTRL (CECTRL),
268 .CED (CED),
269 .CEINMODE (CEINMODE),
270 .CEM (CEM),
271 .CEP (CEP),
272 .CLK (CLK),
273 .D (D),
274 .INMODE (INMODE),
275 .MULTSIGNIN (MULTSIGNIN),
276 .OPMODE (OPMODE),
277 .PCIN (PCIN),
278 .RSTA (RSTA),
279 .RSTALLCARRYIN (RSTALLCARRYIN),
280 .RSTALUMODE (RSTALUMODE),
281 .RSTB (RSTB),
282 .RSTC (RSTC),
283 .RSTCTRL (RSTCTRL),
284 .RSTD (RSTD),
285 .RSTINMODE (RSTINMODE),
286 .RSTM (RSTM),
287 .RSTP (RSTP)
288 );
289
290 DSP48E1_UUT #(
291 .ACASCREG (ACASCREG),
292 .ADREG (ADREG),
293 .ALUMODEREG (ALUMODEREG),
294 .AREG (AREG),
295 .AUTORESET_PATDET (AUTORESET_PATDET),
296 .A_INPUT (A_INPUT),
297 .BCASCREG (BCASCREG),
298 .BREG (BREG),
299 .B_INPUT (B_INPUT),
300 .CARRYINREG (CARRYINREG),
301 .CARRYINSELREG (CARRYINSELREG),
302 .CREG (CREG),
303 .DREG (DREG),
304 .INMODEREG (INMODEREG),
305 .MREG (MREG),
306 .OPMODEREG (OPMODEREG),
307 .PREG (PREG),
308 .SEL_MASK (SEL_MASK),
309 .SEL_PATTERN (SEL_PATTERN),
310 .USE_DPORT (USE_DPORT),
311 .USE_MULT (USE_MULT),
312 .USE_PATTERN_DETECT (USE_PATTERN_DETECT),
313 .USE_SIMD (USE_SIMD),
314 .MASK (MASK),
315 .PATTERN (PATTERN),
316 .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
317 .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
318 .IS_CLK_INVERTED (IS_CLK_INVERTED),
319 .IS_INMODE_INVERTED (IS_INMODE_INVERTED),
320 .IS_OPMODE_INVERTED (IS_OPMODE_INVERTED)
321 ) uut (
322 .ACOUT (ACOUT),
323 .BCOUT (BCOUT),
324 .CARRYCASCOUT (CARRYCASCOUT),
325 .CARRYOUT (CARRYOUT),
326 .MULTSIGNOUT (MULTSIGNOUT),
327 .OVERFLOW (OVERFLOW),
328 .P (P),
329 .PATTERNBDETECT(PATTERNBDETECT),
330 .PATTERNDETECT (PATTERNDETECT),
331 .PCOUT (PCOUT),
332 .UNDERFLOW (UNDERFLOW),
333 .A (A),
334 .ACIN (ACIN),
335 .ALUMODE (ALUMODE),
336 .B (B),
337 .BCIN (BCIN),
338 .C (C),
339 .CARRYCASCIN (CARRYCASCIN),
340 .CARRYINSEL (CARRYINSEL),
341 .CEA1 (CEA1),
342 .CEA2 (CEA2),
343 .CEAD (CEAD),
344 .CEALUMODE (CEALUMODE),
345 .CEB1 (CEB1),
346 .CEB2 (CEB2),
347 .CEC (CEC),
348 .CECARRYIN (CECARRYIN),
349 .CECTRL (CECTRL),
350 .CED (CED),
351 .CEINMODE (CEINMODE),
352 .CEM (CEM),
353 .CEP (CEP),
354 .CLK (CLK),
355 .D (D),
356 .INMODE (INMODE),
357 .MULTSIGNIN (MULTSIGNIN),
358 .OPMODE (OPMODE),
359 .PCIN (PCIN),
360 .RSTA (RSTA),
361 .RSTALLCARRYIN (RSTALLCARRYIN),
362 .RSTALUMODE (RSTALUMODE),
363 .RSTB (RSTB),
364 .RSTC (RSTC),
365 .RSTCTRL (RSTCTRL),
366 .RSTD (RSTD),
367 .RSTINMODE (RSTINMODE),
368 .RSTM (RSTM),
369 .RSTP (RSTP)
370 );
371 endmodule
372
373 module mult_noreg_nopreadd_nocasc;
374 testbench #(
375 .ACASCREG (0),
376 .ADREG (0),
377 .ALUMODEREG (0),
378 .AREG (0),
379 .AUTORESET_PATDET ("NO_RESET"),
380 .A_INPUT ("DIRECT"),
381 .BCASCREG (0),
382 .BREG (0),
383 .B_INPUT ("DIRECT"),
384 .CARRYINREG (0),
385 .CARRYINSELREG (0),
386 .CREG (0),
387 .DREG (0),
388 .INMODEREG (0),
389 .MREG (0),
390 .OPMODEREG (0),
391 .PREG (0),
392 .SEL_MASK ("MASK"),
393 .SEL_PATTERN ("PATTERN"),
394 .USE_DPORT ("FALSE"),
395 .USE_MULT ("DYNAMIC"),
396 .USE_PATTERN_DETECT ("NO_PATDET"),
397 .USE_SIMD ("ONE48"),
398 .MASK (48'h3FFFFFFFFFFF),
399 .PATTERN (48'h000000000000),
400 .IS_ALUMODE_INVERTED(4'b0),
401 .IS_CARRYIN_INVERTED(1'b0),
402 .IS_CLK_INVERTED (1'b0),
403 .IS_INMODE_INVERTED (5'b0),
404 .IS_OPMODE_INVERTED (7'b0)
405 ) testbench ();
406 endmodule
407
408 module mult_allreg_nopreadd_nocasc;
409 testbench #(
410 .ACASCREG (1),
411 .ADREG (1),
412 .ALUMODEREG (1),
413 .AREG (2),
414 .AUTORESET_PATDET ("NO_RESET"),
415 .A_INPUT ("DIRECT"),
416 .BCASCREG (1),
417 .BREG (2),
418 .B_INPUT ("DIRECT"),
419 .CARRYINREG (1),
420 .CARRYINSELREG (1),
421 .CREG (1),
422 .DREG (1),
423 .INMODEREG (1),
424 .MREG (1),
425 .OPMODEREG (1),
426 .PREG (1),
427 .SEL_MASK ("MASK"),
428 .SEL_PATTERN ("PATTERN"),
429 .USE_DPORT ("FALSE"),
430 .USE_MULT ("DYNAMIC"),
431 .USE_PATTERN_DETECT ("NO_PATDET"),
432 .USE_SIMD ("ONE48"),
433 .MASK (48'h3FFFFFFFFFFF),
434 .PATTERN (48'h000000000000),
435 .IS_ALUMODE_INVERTED(4'b0),
436 .IS_CARRYIN_INVERTED(1'b0),
437 .IS_CLK_INVERTED (1'b0),
438 .IS_INMODE_INVERTED (5'b0),
439 .IS_OPMODE_INVERTED (7'b0)
440 ) testbench ();
441 endmodule
442
443 module mult_noreg_preadd_nocasc;
444 testbench #(
445 .ACASCREG (0),
446 .ADREG (0),
447 .ALUMODEREG (0),
448 .AREG (0),
449 .AUTORESET_PATDET ("NO_RESET"),
450 .A_INPUT ("DIRECT"),
451 .BCASCREG (0),
452 .BREG (0),
453 .B_INPUT ("DIRECT"),
454 .CARRYINREG (0),
455 .CARRYINSELREG (0),
456 .CREG (0),
457 .DREG (0),
458 .INMODEREG (0),
459 .MREG (0),
460 .OPMODEREG (0),
461 .PREG (0),
462 .SEL_MASK ("MASK"),
463 .SEL_PATTERN ("PATTERN"),
464 .USE_DPORT ("TRUE"),
465 .USE_MULT ("DYNAMIC"),
466 .USE_PATTERN_DETECT ("NO_PATDET"),
467 .USE_SIMD ("ONE48"),
468 .MASK (48'h3FFFFFFFFFFF),
469 .PATTERN (48'h000000000000),
470 .IS_ALUMODE_INVERTED(4'b0),
471 .IS_CARRYIN_INVERTED(1'b0),
472 .IS_CLK_INVERTED (1'b0),
473 .IS_INMODE_INVERTED (5'b0),
474 .IS_OPMODE_INVERTED (7'b0)
475 ) testbench ();
476 endmodule
477
478 module mult_allreg_preadd_nocasc;
479 testbench #(
480 .ACASCREG (1),
481 .ADREG (1),
482 .ALUMODEREG (1),
483 .AREG (2),
484 .AUTORESET_PATDET ("NO_RESET"),
485 .A_INPUT ("DIRECT"),
486 .BCASCREG (1),
487 .BREG (2),
488 .B_INPUT ("DIRECT"),
489 .CARRYINREG (1),
490 .CARRYINSELREG (1),
491 .CREG (1),
492 .DREG (1),
493 .INMODEREG (1),
494 .MREG (1),
495 .OPMODEREG (1),
496 .PREG (1),
497 .SEL_MASK ("MASK"),
498 .SEL_PATTERN ("PATTERN"),
499 .USE_DPORT ("TRUE"),
500 .USE_MULT ("DYNAMIC"),
501 .USE_PATTERN_DETECT ("NO_PATDET"),
502 .USE_SIMD ("ONE48"),
503 .MASK (48'h3FFFFFFFFFFF),
504 .PATTERN (48'h000000000000),
505 .IS_ALUMODE_INVERTED(4'b0),
506 .IS_CARRYIN_INVERTED(1'b0),
507 .IS_CLK_INVERTED (1'b0),
508 .IS_INMODE_INVERTED (5'b0),
509 .IS_OPMODE_INVERTED (7'b0)
510 ) testbench ();
511 endmodule
512
513 module mult_inreg_preadd_nocasc;
514 testbench #(
515 .ACASCREG (1),
516 .ADREG (0),
517 .ALUMODEREG (0),
518 .AREG (1),
519 .AUTORESET_PATDET ("NO_RESET"),
520 .A_INPUT ("DIRECT"),
521 .BCASCREG (1),
522 .BREG (1),
523 .B_INPUT ("DIRECT"),
524 .CARRYINREG (0),
525 .CARRYINSELREG (0),
526 .CREG (1),
527 .DREG (1),
528 .INMODEREG (0),
529 .MREG (0),
530 .OPMODEREG (0),
531 .PREG (0),
532 .SEL_MASK ("MASK"),
533 .SEL_PATTERN ("PATTERN"),
534 .USE_DPORT ("TRUE"),
535 .USE_MULT ("DYNAMIC"),
536 .USE_PATTERN_DETECT ("NO_PATDET"),
537 .USE_SIMD ("ONE48"),
538 .MASK (48'h3FFFFFFFFFFF),
539 .PATTERN (48'h000000000000),
540 .IS_ALUMODE_INVERTED(4'b0),
541 .IS_CARRYIN_INVERTED(1'b0),
542 .IS_CLK_INVERTED (1'b0),
543 .IS_INMODE_INVERTED (5'b0),
544 .IS_OPMODE_INVERTED (7'b0)
545 ) testbench ();
546 endmodule
547
548 module simd12_preadd_noreg_nocasc;
549 testbench #(
550 .ACASCREG (0),
551 .ADREG (0),
552 .ALUMODEREG (0),
553 .AREG (0),
554 .AUTORESET_PATDET ("NO_RESET"),
555 .A_INPUT ("DIRECT"),
556 .BCASCREG (0),
557 .BREG (0),
558 .B_INPUT ("DIRECT"),
559 .CARRYINREG (0),
560 .CARRYINSELREG (0),
561 .CREG (0),
562 .DREG (0),
563 .INMODEREG (0),
564 .MREG (0),
565 .OPMODEREG (0),
566 .PREG (0),
567 .SEL_MASK ("MASK"),
568 .SEL_PATTERN ("PATTERN"),
569 .USE_DPORT ("TRUE"),
570 .USE_MULT ("DYNAMIC"),
571 .USE_PATTERN_DETECT ("NO_PATDET"),
572 .USE_SIMD ("FOUR12"),
573 .MASK (48'h3FFFFFFFFFFF),
574 .PATTERN (48'h000000000000),
575 .IS_ALUMODE_INVERTED(4'b0),
576 .IS_CARRYIN_INVERTED(1'b0),
577 .IS_CLK_INVERTED (1'b0),
578 .IS_INMODE_INVERTED (5'b0),
579 .IS_OPMODE_INVERTED (7'b0)
580 ) testbench ();
581 endmodule
582
583
584 module simd24_preadd_noreg_nocasc;
585 testbench #(
586 .ACASCREG (0),
587 .ADREG (0),
588 .ALUMODEREG (0),
589 .AREG (0),
590 .AUTORESET_PATDET ("NO_RESET"),
591 .A_INPUT ("DIRECT"),
592 .BCASCREG (0),
593 .BREG (0),
594 .B_INPUT ("DIRECT"),
595 .CARRYINREG (0),
596 .CARRYINSELREG (0),
597 .CREG (0),
598 .DREG (0),
599 .INMODEREG (0),
600 .MREG (0),
601 .OPMODEREG (0),
602 .PREG (0),
603 .SEL_MASK ("MASK"),
604 .SEL_PATTERN ("PATTERN"),
605 .USE_DPORT ("TRUE"),
606 .USE_MULT ("DYNAMIC"),
607 .USE_PATTERN_DETECT ("NO_PATDET"),
608 .USE_SIMD ("TWO24"),
609 .MASK (48'h3FFFFFFFFFFF),
610 .PATTERN (48'h000000000000),
611 .IS_ALUMODE_INVERTED(4'b0),
612 .IS_CARRYIN_INVERTED(1'b0),
613 .IS_CLK_INVERTED (1'b0),
614 .IS_INMODE_INVERTED (5'b0),
615 .IS_OPMODE_INVERTED (7'b0)
616 ) testbench ();
617 endmodule
618
619 module macc_overflow_underflow;
620 testbench #(
621 .ACASCREG (0),
622 .ADREG (0),
623 .ALUMODEREG (0),
624 .AREG (0),
625 .AUTORESET_PATDET ("NO_RESET"),
626 .A_INPUT ("DIRECT"),
627 .BCASCREG (0),
628 .BREG (0),
629 .B_INPUT ("DIRECT"),
630 .CARRYINREG (0),
631 .CARRYINSELREG (0),
632 .CREG (0),
633 .DREG (0),
634 .INMODEREG (0),
635 .MREG (0),
636 .OPMODEREG (0),
637 .PREG (1),
638 .SEL_MASK ("MASK"),
639 .SEL_PATTERN ("PATTERN"),
640 .USE_DPORT ("FALSE"),
641 .USE_MULT ("DYNAMIC"),
642 .USE_PATTERN_DETECT ("PATDET"),
643 .USE_SIMD ("ONE48"),
644 .MASK (48'h1FFFFFFFFFFF),
645 .PATTERN (48'h000000000000),
646 .IS_ALUMODE_INVERTED(4'b0),
647 .IS_CARRYIN_INVERTED(1'b0),
648 .IS_CLK_INVERTED (1'b0),
649 .IS_INMODE_INVERTED (5'b0),
650 .IS_OPMODE_INVERTED (7'b0)
651 ) testbench ();
652 endmodule