techlibs/xilinx/xc2v_brams_map.v

   1 // Virtex 2, Virtex 2 Pro, Spartan 3, Spartan 3E, Spartan 3A block RAM
   2 // mapping (Spartan 3A is a superset of the other four).
   3
   4 // ------------------------------------------------------------------------
   5
   6 module \$__XILINX_RAMB16 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
   7         parameter CFG_ABITS = 9;
   8         parameter CFG_DBITS = 36;
   9         parameter CFG_ENABLE_B = 1;
  10
  11         parameter CLKPOL2 = 1;
  12         parameter CLKPOL3 = 1;
  13         parameter [18431:0] INIT = 18432'bx;
  14
  15         input CLK2;
  16         input CLK3;
  17
  18         input [CFG_ABITS-1:0] A1ADDR;
  19         output [CFG_DBITS-1:0] A1DATA;
  20         input A1EN;
  21
  22         input [CFG_ABITS-1:0] B1ADDR;
  23         input [CFG_DBITS-1:0] B1DATA;
  24         input [CFG_ENABLE_B-1:0] B1EN;
  25
  26         generate if (CFG_DBITS == 1) begin
  27                 wire DOB;
  28                 RAMB16_S1_S1 #(
  29                         `include "brams_init_16.vh"
  30                         .WRITE_MODE_A("READ_FIRST"),
  31                         .WRITE_MODE_B("READ_FIRST"),
  32                 ) _TECHMAP_REPLACE_ (
  33                         .DIA(1'd0),
  34                         .DOA(A1DATA),
  35                         .ADDRA(A1ADDR),
  36                         .CLKA(CLK2 ^ !CLKPOL2),
  37                         .ENA(A1EN),
  38                         .SSRA(|0),
  39                         .WEA(1'b0),
  40
  41                         .DIB(B1DATA),
  42                         .DOB(DOB),
  43                         .ADDRB(B1ADDR),
  44                         .CLKB(CLK3 ^ !CLKPOL3),
  45                         .ENB(|1),
  46                         .SSRB(|0),
  47                         .WEB(B1EN)
  48                 );
  49         end else if (CFG_DBITS == 2) begin
  50                 wire [1:0] DOB;
  51                 RAMB16_S2_S2 #(
  52                         `include "brams_init_16.vh"
  53                         .WRITE_MODE_A("READ_FIRST"),
  54                         .WRITE_MODE_B("READ_FIRST"),
  55                 ) _TECHMAP_REPLACE_ (
  56                         .DIA(2'd0),
  57                         .DOA(A1DATA),
  58                         .ADDRA(A1ADDR),
  59                         .CLKA(CLK2 ^ !CLKPOL2),
  60                         .ENA(A1EN),
  61                         .SSRA(|0),
  62                         .WEA(1'b0),
  63
  64                         .DIB(B1DATA),
  65                         .DOB(DOB),
  66                         .ADDRB(B1ADDR),
  67                         .CLKB(CLK3 ^ !CLKPOL3),
  68                         .ENB(|1),
  69                         .SSRB(|0),
  70                         .WEB(B1EN)
  71                 );
  72         end else if (CFG_DBITS == 4) begin
  73                 wire [3:0] DOB;
  74                 RAMB16_S4_S4 #(
  75                         `include "brams_init_16.vh"
  76                         .WRITE_MODE_A("READ_FIRST"),
  77                         .WRITE_MODE_B("READ_FIRST"),
  78                 ) _TECHMAP_REPLACE_ (
  79                         .DIA(4'd0),
  80                         .DOA(A1DATA),
  81                         .ADDRA(A1ADDR),
  82                         .CLKA(CLK2 ^ !CLKPOL2),
  83                         .ENA(A1EN),
  84                         .SSRA(|0),
  85                         .WEA(1'b0),
  86
  87                         .DIB(B1DATA),
  88                         .DOB(DOB),
  89                         .ADDRB(B1ADDR),
  90                         .CLKB(CLK3 ^ !CLKPOL3),
  91                         .ENB(|1),
  92                         .SSRB(|0),
  93                         .WEB(B1EN)
  94                 );
  95         end else if (CFG_DBITS == 9) begin
  96                 wire [7:0] DOB;
  97                 wire DOPB;
  98                 RAMB16_S9_S9 #(
  99                         `include "brams_init_18.vh"
 100                         .WRITE_MODE_A("READ_FIRST"),
 101                         .WRITE_MODE_B("READ_FIRST"),
 102                 ) _TECHMAP_REPLACE_ (
 103                         .DIA(8'd0),
 104                         .DIPA(1'd0),
 105                         .DOA(A1DATA[7:0]),
 106                         .DOPA(A1DATA[8]),
 107                         .ADDRA(A1ADDR),
 108                         .CLKA(CLK2 ^ !CLKPOL2),
 109                         .ENA(A1EN),
 110                         .SSRA(|0),
 111                         .WEA(1'b0),
 112
 113                         .DIB(B1DATA[7:0]),
 114                         .DIPB(B1DATA[8]),
 115                         .DOB(DOB),
 116                         .DOPB(DOPB),
 117                         .ADDRB(B1ADDR),
 118                         .CLKB(CLK3 ^ !CLKPOL3),
 119                         .ENB(|1),
 120                         .SSRB(|0),
 121                         .WEB(B1EN)
 122                 );
 123         end else if (CFG_DBITS == 18) begin
 124                 wire [15:0] DOB;
 125                 wire [1:0] DOPB;
 126                 RAMB16_S18_S18 #(
 127                         `include "brams_init_18.vh"
 128                         .WRITE_MODE_A("READ_FIRST"),
 129                         .WRITE_MODE_B("READ_FIRST"),
 130                 ) _TECHMAP_REPLACE_ (
 131                         .DIA(16'd0),
 132                         .DIPA(2'd0),
 133                         .DOA({A1DATA[16:9], A1DATA[7:0]}),
 134                         .DOPA({A1DATA[17], A1DATA[8]}),
 135                         .ADDRA(A1ADDR),
 136                         .CLKA(CLK2 ^ !CLKPOL2),
 137                         .ENA(A1EN),
 138                         .SSRA(|0),
 139                         .WEA(1'b0),
 140
 141                         .DIB({B1DATA[16:9], B1DATA[7:0]}),
 142                         .DIPB({B1DATA[17], B1DATA[8]}),
 143                         .DOB(DOB),
 144                         .DOPB(DOPB),
 145                         .ADDRB(B1ADDR),
 146                         .CLKB(CLK3 ^ !CLKPOL3),
 147                         .ENB(|1),
 148                         .SSRB(|0),
 149                         .WEB(B1EN)
 150                 );
 151         end else if (CFG_DBITS == 36) begin
 152                 wire [31:0] DOB;
 153                 wire [3:0] DOPB;
 154                 RAMB16_S36_S36 #(
 155                         `include "brams_init_18.vh"
 156                         .WRITE_MODE_A("READ_FIRST"),
 157                         .WRITE_MODE_B("READ_FIRST"),
 158                 ) _TECHMAP_REPLACE_ (
 159                         .DIA(32'd0),
 160                         .DIPA(4'd0),
 161                         .DOA({A1DATA[34:27], A1DATA[25:18], A1DATA[16:9], A1DATA[7:0]}),
 162                         .DOPA({A1DATA[35], A1DATA[26], A1DATA[17], A1DATA[8]}),
 163                         .ADDRA(A1ADDR),
 164                         .CLKA(CLK2 ^ !CLKPOL2),
 165                         .ENA(A1EN),
 166                         .SSRA(|0),
 167                         .WEA(1'b0),
 168
 169                         .DIB({B1DATA[34:27], B1DATA[25:18], B1DATA[16:9], B1DATA[7:0]}),
 170                         .DIPB({B1DATA[35], B1DATA[26], B1DATA[17], B1DATA[8]}),
 171                         .DOB(DOB),
 172                         .DOPB(DOPB),
 173                         .ADDRB(B1ADDR),
 174                         .CLKB(CLK3 ^ !CLKPOL3),
 175                         .ENB(|1),
 176                         .SSRB(|0),
 177                         .WEB(B1EN)
 178                 );
 179         end else begin
 180                 $error("Strange block RAM data width.");
 181         end endgenerate
 182 endmodule
 183
 184
 185 // Version with separate byte enables, only available on Spartan 3A.
 186
 187 module \$__XILINX_RAMB16BWE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 188         parameter CFG_ABITS = 9;
 189         parameter CFG_DBITS = 36;
 190         parameter CFG_ENABLE_B = 4;
 191
 192         parameter CLKPOL2 = 1;
 193         parameter CLKPOL3 = 1;
 194         parameter [18431:0] INIT = 18432'bx;
 195
 196         input CLK2;
 197         input CLK3;
 198
 199         input [CFG_ABITS-1:0] A1ADDR;
 200         output [CFG_DBITS-1:0] A1DATA;
 201         input A1EN;
 202
 203         input [CFG_ABITS-1:0] B1ADDR;
 204         input [CFG_DBITS-1:0] B1DATA;
 205         input [CFG_ENABLE_B-1:0] B1EN;
 206
 207         generate if (CFG_DBITS == 18) begin
 208                 wire [15:0] DOB;
 209                 wire [1:0] DOPB;
 210                 RAMB16BWE_S18_S18 #(
 211                         `include "brams_init_18.vh"
 212                         .WRITE_MODE_A("READ_FIRST"),
 213                         .WRITE_MODE_B("READ_FIRST"),
 214                 ) _TECHMAP_REPLACE_ (
 215                         .DIA(16'd0),
 216                         .DIPA(2'd0),
 217                         .DOA({A1DATA[16:9], A1DATA[7:0]}),
 218                         .DOPA({A1DATA[17], A1DATA[8]}),
 219                         .ADDRA(A1ADDR),
 220                         .CLKA(CLK2 ^ !CLKPOL2),
 221                         .ENA(A1EN),
 222                         .SSRA(|0),
 223                         .WEA(2'b00),
 224
 225                         .DIB({B1DATA[16:9], B1DATA[7:0]}),
 226                         .DIPB({B1DATA[17], B1DATA[8]}),
 227                         .DOB(DOB),
 228                         .DOPB(DOPB),
 229                         .ADDRB(B1ADDR),
 230                         .CLKB(CLK3 ^ !CLKPOL3),
 231                         .ENB(|1),
 232                         .SSRB(|0),
 233                         .WEB(B1EN)
 234                 );
 235         end else if (CFG_DBITS == 36) begin
 236                 wire [31:0] DOB;
 237                 wire [3:0] DOPB;
 238                 RAMB16BWE_S36_S36 #(
 239                         `include "brams_init_18.vh"
 240                         .WRITE_MODE_A("READ_FIRST"),
 241                         .WRITE_MODE_B("READ_FIRST"),
 242                 ) _TECHMAP_REPLACE_ (
 243                         .DIA(32'd0),
 244                         .DIPA(4'd0),
 245                         .DOA({A1DATA[34:27], A1DATA[25:18], A1DATA[16:9], A1DATA[7:0]}),
 246                         .DOPA({A1DATA[35], A1DATA[26], A1DATA[17], A1DATA[8]}),
 247                         .ADDRA(A1ADDR),
 248                         .CLKA(CLK2 ^ !CLKPOL2),
 249                         .ENA(A1EN),
 250                         .SSRA(|0),
 251                         .WEA(4'b0000),
 252
 253                         .DIB({B1DATA[34:27], B1DATA[25:18], B1DATA[16:9], B1DATA[7:0]}),
 254                         .DIPB({B1DATA[35], B1DATA[26], B1DATA[17], B1DATA[8]}),
 255                         .DOB(DOB),
 256                         .DOPB(DOPB),
 257                         .ADDRB(B1ADDR),
 258                         .CLKB(CLK3 ^ !CLKPOL3),
 259                         .ENB(|1),
 260                         .SSRB(|0),
 261                         .WEB(B1EN)
 262                 );
 263         end else begin
 264                 $error("Strange block RAM data width.");
 265         end endgenerate
 266 endmodule