1 // Virtex 2, Virtex 2 Pro, Spartan 3, Spartan 3E, Spartan 3A block RAM
2 // mapping (Spartan 3A is a superset of the other four).
4 // ------------------------------------------------------------------------
6 module \$__XILINX_RAMB16 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
7 parameter CFG_ABITS = 9;
8 parameter CFG_DBITS = 36;
9 parameter CFG_ENABLE_B = 1;
11 parameter CLKPOL2 = 1;
12 parameter CLKPOL3 = 1;
13 parameter [18431:0] INIT = 18432'bx;
18 input [CFG_ABITS-1:0] A1ADDR;
19 output [CFG_DBITS-1:0] A1DATA;
22 input [CFG_ABITS-1:0] B1ADDR;
23 input [CFG_DBITS-1:0] B1DATA;
24 input [CFG_ENABLE_B-1:0] B1EN;
26 generate if (CFG_DBITS == 1) begin
29 `include "brams_init_16.vh"
30 .WRITE_MODE_A("READ_FIRST"),
31 .WRITE_MODE_B("READ_FIRST"),
36 .CLKA(CLK2 ^ !CLKPOL2),
44 .CLKB(CLK3 ^ !CLKPOL3),
49 end else if (CFG_DBITS == 2) begin
52 `include "brams_init_16.vh"
53 .WRITE_MODE_A("READ_FIRST"),
54 .WRITE_MODE_B("READ_FIRST"),
59 .CLKA(CLK2 ^ !CLKPOL2),
67 .CLKB(CLK3 ^ !CLKPOL3),
72 end else if (CFG_DBITS == 4) begin
75 `include "brams_init_16.vh"
76 .WRITE_MODE_A("READ_FIRST"),
77 .WRITE_MODE_B("READ_FIRST"),
82 .CLKA(CLK2 ^ !CLKPOL2),
90 .CLKB(CLK3 ^ !CLKPOL3),
95 end else if (CFG_DBITS == 9) begin
99 `include "brams_init_18.vh"
100 .WRITE_MODE_A("READ_FIRST"),
101 .WRITE_MODE_B("READ_FIRST"),
102 ) _TECHMAP_REPLACE_ (
108 .CLKA(CLK2 ^ !CLKPOL2),
118 .CLKB(CLK3 ^ !CLKPOL3),
123 end else if (CFG_DBITS == 18) begin
127 `include "brams_init_18.vh"
128 .WRITE_MODE_A("READ_FIRST"),
129 .WRITE_MODE_B("READ_FIRST"),
130 ) _TECHMAP_REPLACE_ (
133 .DOA({A1DATA[16:9], A1DATA[7:0]}),
134 .DOPA({A1DATA[17], A1DATA[8]}),
136 .CLKA(CLK2 ^ !CLKPOL2),
141 .DIB({B1DATA[16:9], B1DATA[7:0]}),
142 .DIPB({B1DATA[17], B1DATA[8]}),
146 .CLKB(CLK3 ^ !CLKPOL3),
151 end else if (CFG_DBITS == 36) begin
155 `include "brams_init_18.vh"
156 .WRITE_MODE_A("READ_FIRST"),
157 .WRITE_MODE_B("READ_FIRST"),
158 ) _TECHMAP_REPLACE_ (
161 .DOA({A1DATA[34:27], A1DATA[25:18], A1DATA[16:9], A1DATA[7:0]}),
162 .DOPA({A1DATA[35], A1DATA[26], A1DATA[17], A1DATA[8]}),
164 .CLKA(CLK2 ^ !CLKPOL2),
169 .DIB({B1DATA[34:27], B1DATA[25:18], B1DATA[16:9], B1DATA[7:0]}),
170 .DIPB({B1DATA[35], B1DATA[26], B1DATA[17], B1DATA[8]}),
174 .CLKB(CLK3 ^ !CLKPOL3),
180 $error("Strange block RAM data width.");
185 // Version with separate byte enables, only available on Spartan 3A.
187 module \$__XILINX_RAMB16BWE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
188 parameter CFG_ABITS = 9;
189 parameter CFG_DBITS = 36;
190 parameter CFG_ENABLE_B = 4;
192 parameter CLKPOL2 = 1;
193 parameter CLKPOL3 = 1;
194 parameter [18431:0] INIT = 18432'bx;
199 input [CFG_ABITS-1:0] A1ADDR;
200 output [CFG_DBITS-1:0] A1DATA;
203 input [CFG_ABITS-1:0] B1ADDR;
204 input [CFG_DBITS-1:0] B1DATA;
205 input [CFG_ENABLE_B-1:0] B1EN;
207 generate if (CFG_DBITS == 18) begin
211 `include "brams_init_18.vh"
212 .WRITE_MODE_A("READ_FIRST"),
213 .WRITE_MODE_B("READ_FIRST"),
214 ) _TECHMAP_REPLACE_ (
217 .DOA({A1DATA[16:9], A1DATA[7:0]}),
218 .DOPA({A1DATA[17], A1DATA[8]}),
220 .CLKA(CLK2 ^ !CLKPOL2),
225 .DIB({B1DATA[16:9], B1DATA[7:0]}),
226 .DIPB({B1DATA[17], B1DATA[8]}),
230 .CLKB(CLK3 ^ !CLKPOL3),
235 end else if (CFG_DBITS == 36) begin
239 `include "brams_init_18.vh"
240 .WRITE_MODE_A("READ_FIRST"),
241 .WRITE_MODE_B("READ_FIRST"),
242 ) _TECHMAP_REPLACE_ (
245 .DOA({A1DATA[34:27], A1DATA[25:18], A1DATA[16:9], A1DATA[7:0]}),
246 .DOPA({A1DATA[35], A1DATA[26], A1DATA[17], A1DATA[8]}),
248 .CLKA(CLK2 ^ !CLKPOL2),
253 .DIB({B1DATA[34:27], B1DATA[25:18], B1DATA[16:9], B1DATA[7:0]}),
254 .DIPB({B1DATA[35], B1DATA[26], B1DATA[17], B1DATA[8]}),
258 .CLKB(CLK3 ^ !CLKPOL3),
264 $error("Strange block RAM data width.");