techlibs/xilinx/xc5v_dsp_map.v

   1 module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
   2         parameter A_SIGNED = 0;
   3         parameter B_SIGNED = 0;
   4         parameter A_WIDTH = 0;
   5         parameter B_WIDTH = 0;
   6         parameter Y_WIDTH = 0;
   7
   8         wire [47:0] P_48;
   9         DSP48E #(
  10                 // Disable all registers
  11                 .ACASCREG(0),
  12                 .A_INPUT("DIRECT"),
  13                 .ALUMODEREG(0),
  14                 .AREG(0),
  15                 .BCASCREG(0),
  16                 .B_INPUT("DIRECT"),
  17                 .BREG(0),
  18                 .MULTCARRYINREG(0),
  19                 .CARRYINREG(0),
  20                 .CARRYINSELREG(0),
  21                 .CREG(0),
  22                 .MREG(0),
  23                 .OPMODEREG(0),
  24                 .PREG(0),
  25                 .USE_MULT("MULT"),
  26                 .USE_SIMD("ONE48")
  27         ) _TECHMAP_REPLACE_ (
  28                 //Data path
  29                 .A({{5{A[24]}}, A}),
  30                 .B(B),
  31                 .C(48'b0),
  32                 .P(P_48),
  33
  34                 .ALUMODE(4'b0000),
  35                 .OPMODE(7'b000101),
  36                 .CARRYINSEL(3'b000),
  37
  38                 .ACIN(30'b0),
  39                 .BCIN(18'b0),
  40                 .PCIN(48'b0),
  41                 .CARRYIN(1'b0)
  42         );
  43         assign Y = P_48;
  44 endmodule
  45