Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors
[yosys.git] / techlibs / xilinx / xc6s_brams.txt
1
2 bram $__XILINX_RAMB8BWER_SDP
3 init 1
4 abits 8
5 dbits 36
6 groups 2
7 ports 1 1
8 wrmode 0 1
9 enable 1 4
10 transp 0 0
11 clocks 2 3
12 clkpol 2 3
13 endbram
14
15 bram $__XILINX_RAMB16BWER_TDP
16 init 1
17 abits 9 @a9d36
18 dbits 36 @a9d36
19 abits 10 @a10d18
20 dbits 18 @a10d18
21 abits 11 @a11d9
22 dbits 9 @a11d9
23 abits 12 @a12d4
24 dbits 4 @a12d4
25 abits 13 @a13d2
26 dbits 2 @a13d2
27 abits 14 @a14d1
28 dbits 1 @a14d1
29 groups 2
30 ports 1 1
31 wrmode 0 1
32 enable 1 4 @a9d36
33 enable 1 2 @a10d18
34 enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
35 transp 0 0
36 clocks 2 3
37 clkpol 2 3
38 endbram
39
40 bram $__XILINX_RAMB8BWER_TDP
41 init 1
42 abits 9 @a9d18
43 dbits 18 @a9d18
44 abits 10 @a10d9
45 dbits 9 @a10d9
46 abits 11 @a11d4
47 dbits 4 @a11d4
48 abits 12 @a12d2
49 dbits 2 @a12d2
50 abits 13 @a13d1
51 dbits 1 @a13d1
52 groups 2
53 ports 1 1
54 wrmode 0 1
55 enable 1 2 @a9d18
56 enable 1 1 @a10d9 @a11d4 @a12d2 @a13d1
57 transp 0 0
58 clocks 2 3
59 clkpol 2 3
60 endbram
61
62 match $__XILINX_RAMB8BWER_SDP
63 min bits 4096
64 min efficiency 5
65 shuffle_enable B
66 make_transp
67 or_next_if_better
68 endmatch
69
70 match $__XILINX_RAMB16BWER_TDP
71 min bits 4096
72 min efficiency 5
73 shuffle_enable B
74 make_transp
75 or_next_if_better
76 endmatch
77
78 match $__XILINX_RAMB8BWER_TDP
79 min bits 4096
80 min efficiency 5
81 shuffle_enable B
82 make_transp
83 endmatch
84