techlibs/xilinx/xc6s_brams_map.v

   1 module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
   2         parameter CLKPOL2 = 1;
   3         parameter CLKPOL3 = 1;
   4         parameter [9215:0] INIT = 9216'bx;
   5
   6         input CLK2;
   7         input CLK3;
   8
   9         input [7:0] A1ADDR;
  10         output [35:0] A1DATA;
  11         input A1EN;
  12
  13         input [7:0] B1ADDR;
  14         input [35:0] B1DATA;
  15         input [3:0] B1EN;
  16
  17         wire [12:0] A1ADDR_13 = {A1ADDR, 5'b0};
  18         wire [12:0] B1ADDR_13 = {B1ADDR, 5'b0};
  19
  20         wire [3:0] DIP, DOP;
  21         wire [31:0] DI, DO;
  22
  23         assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
  24         assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
  25
  26         RAMB8BWER #(
  27                 .RAM_MODE("SDP"),
  28                 .DATA_WIDTH_A(36),
  29                 .DATA_WIDTH_B(36),
  30                 .WRITE_MODE_A("READ_FIRST"),
  31                 .WRITE_MODE_B("READ_FIRST"),
  32                 `include "brams_init_9.vh"
  33         ) _TECHMAP_REPLACE_ (
  34                 .DOBDO(DO[31:16]),
  35                 .DOADO(DO[15:0]),
  36                 .DOPBDOP(DOP[3:2]),
  37                 .DOPADOP(DOP[1:0]),
  38                 .DIBDI(DI[31:16]),
  39                 .DIADI(DI[15:0]),
  40                 .DIPBDIP(DIP[3:2]),
  41                 .DIPADIP(DIP[1:0]),
  42                 .WEBWEU(B1EN[3:2]),
  43                 .WEAWEL(B1EN[1:0]),
  44
  45                 .ADDRAWRADDR(B1ADDR_13),
  46                 .CLKAWRCLK(CLK3 ^ !CLKPOL3),
  47                 .ENAWREN(|1),
  48                 .REGCEA(|0),
  49                 .RSTA(|0),
  50
  51                 .ADDRBRDADDR(A1ADDR_13),
  52                 .CLKBRDCLK(CLK2 ^ !CLKPOL2),
  53                 .ENBRDEN(A1EN),
  54                 .REGCEBREGCE(|1),
  55                 .RSTBRST(|0)
  56         );
  57 endmodule
  58
  59 // ------------------------------------------------------------------------
  60
  61 module \$__XILINX_RAMB16BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
  62         parameter CFG_ABITS = 9;
  63         parameter CFG_DBITS = 36;
  64         parameter CFG_ENABLE_B = 4;
  65
  66         parameter CLKPOL2 = 1;
  67         parameter CLKPOL3 = 1;
  68         parameter [18431:0] INIT = 18432'bx;
  69
  70         input CLK2;
  71         input CLK3;
  72
  73         input [CFG_ABITS-1:0] A1ADDR;
  74         output [CFG_DBITS-1:0] A1DATA;
  75         input A1EN;
  76
  77         input [CFG_ABITS-1:0] B1ADDR;
  78         input [CFG_DBITS-1:0] B1DATA;
  79         input [CFG_ENABLE_B-1:0] B1EN;
  80
  81         wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
  82         wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
  83         wire [3:0] B1EN_4 = {4{B1EN}};
  84
  85         wire [3:0] DIP, DOP;
  86         wire [31:0] DI, DO;
  87
  88         wire [31:0] DOB;
  89         wire [3:0] DOPB;
  90
  91         assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
  92         assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
  93
  94         generate if (CFG_DBITS > 8) begin
  95                 RAMB16BWER #(
  96                         .DATA_WIDTH_A(CFG_DBITS),
  97                         .DATA_WIDTH_B(CFG_DBITS),
  98                         .WRITE_MODE_A("READ_FIRST"),
  99                         .WRITE_MODE_B("READ_FIRST"),
 100                         `include "brams_init_18.vh"
 101                 ) _TECHMAP_REPLACE_ (
 102                         .DIA(32'd0),
 103                         .DIPA(4'd0),
 104                         .DOA(DO[31:0]),
 105                         .DOPA(DOP[3:0]),
 106                         .ADDRA(A1ADDR_14),
 107                         .CLKA(CLK2 ^ !CLKPOL2),
 108                         .ENA(A1EN),
 109                         .REGCEA(|1),
 110                         .RSTA(|0),
 111                         .WEA(4'b0),
 112
 113                         .DIB(DI),
 114                         .DIPB(DIP),
 115                         .DOB(DOB),
 116                         .DOPB(DOPB),
 117                         .ADDRB(B1ADDR_14),
 118                         .CLKB(CLK3 ^ !CLKPOL3),
 119                         .ENB(|1),
 120                         .REGCEB(|0),
 121                         .RSTB(|0),
 122                         .WEB(B1EN_4)
 123                 );
 124         end else begin
 125                 RAMB16BWER #(
 126                         .DATA_WIDTH_A(CFG_DBITS),
 127                         .DATA_WIDTH_B(CFG_DBITS),
 128                         .WRITE_MODE_A("READ_FIRST"),
 129                         .WRITE_MODE_B("READ_FIRST"),
 130                         `include "brams_init_16.vh"
 131                 ) _TECHMAP_REPLACE_ (
 132                         .DIA(32'd0),
 133                         .DIPA(4'd0),
 134                         .DOA(DO[31:0]),
 135                         .DOPA(DOP[3:0]),
 136                         .ADDRA(A1ADDR_14),
 137                         .CLKA(CLK2 ^ !CLKPOL2),
 138                         .ENA(A1EN),
 139                         .REGCEA(|1),
 140                         .RSTA(|0),
 141                         .WEA(4'b0),
 142
 143                         .DIB(DI),
 144                         .DIPB(DIP),
 145                         .DOB(DOB),
 146                         .DOPB(DOPB),
 147                         .ADDRB(B1ADDR_14),
 148                         .CLKB(CLK3 ^ !CLKPOL3),
 149                         .ENB(|1),
 150                         .REGCEB(|0),
 151                         .RSTB(|0),
 152                         .WEB(B1EN_4)
 153                 );
 154         end endgenerate
 155 endmodule
 156
 157 // ------------------------------------------------------------------------
 158
 159 module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 160         parameter CFG_ABITS = 9;
 161         parameter CFG_DBITS = 18;
 162         parameter CFG_ENABLE_B = 2;
 163
 164         parameter CLKPOL2 = 1;
 165         parameter CLKPOL3 = 1;
 166         parameter [9215:0] INIT = 9216'bx;
 167
 168         input CLK2;
 169         input CLK3;
 170
 171         input [CFG_ABITS-1:0] A1ADDR;
 172         output [CFG_DBITS-1:0] A1DATA;
 173         input A1EN;
 174
 175         input [CFG_ABITS-1:0] B1ADDR;
 176         input [CFG_DBITS-1:0] B1DATA;
 177         input [CFG_ENABLE_B-1:0] B1EN;
 178
 179         wire [12:0] A1ADDR_13 = A1ADDR << (13 - CFG_ABITS);
 180         wire [12:0] B1ADDR_13 = B1ADDR << (13 - CFG_ABITS);
 181         wire [1:0] B1EN_2 = {2{B1EN}};
 182
 183         wire [1:0] DIP, DOP;
 184         wire [15:0] DI, DO;
 185
 186         wire [15:0] DOBDO;
 187         wire [1:0] DOPBDOP;
 188
 189         assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
 190         assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
 191
 192         generate if (CFG_DBITS > 8) begin
 193                 RAMB8BWER #(
 194                         .RAM_MODE("TDP"),
 195                         .DATA_WIDTH_A(CFG_DBITS),
 196                         .DATA_WIDTH_B(CFG_DBITS),
 197                         .WRITE_MODE_A("READ_FIRST"),
 198                         .WRITE_MODE_B("READ_FIRST"),
 199                         `include "brams_init_9.vh"
 200                 ) _TECHMAP_REPLACE_ (
 201                         .DIADI(16'b0),
 202                         .DIPADIP(2'b0),
 203                         .DOADO(DO),
 204                         .DOPADOP(DOP),
 205                         .ADDRAWRADDR(A1ADDR_13),
 206                         .CLKAWRCLK(CLK2 ^ !CLKPOL2),
 207                         .ENAWREN(A1EN),
 208                         .REGCEA(|1),
 209                         .RSTA(|0),
 210                         .WEAWEL(2'b0),
 211
 212                         .DIBDI(DI),
 213                         .DIPBDIP(DIP),
 214                         .DOBDO(DOBDO),
 215                         .DOPBDOP(DOPBDOP),
 216                         .ADDRBRDADDR(B1ADDR_13),
 217                         .CLKBRDCLK(CLK3 ^ !CLKPOL3),
 218                         .ENBRDEN(|1),
 219                         .REGCEBREGCE(|0),
 220                         .RSTBRST(|0),
 221                         .WEBWEU(B1EN_2)
 222                 );
 223         end else begin
 224                 RAMB8BWER #(
 225                         .RAM_MODE("TDP"),
 226                         .DATA_WIDTH_A(CFG_DBITS),
 227                         .DATA_WIDTH_B(CFG_DBITS),
 228                         .WRITE_MODE_A("READ_FIRST"),
 229                         .WRITE_MODE_B("READ_FIRST"),
 230                         `include "brams_init_8.vh"
 231                 ) _TECHMAP_REPLACE_ (
 232                         .DIADI(16'b0),
 233                         .DIPADIP(2'b0),
 234                         .DOADO(DO),
 235                         .DOPADOP(DOP),
 236                         .ADDRAWRADDR(A1ADDR_13),
 237                         .CLKAWRCLK(CLK2 ^ !CLKPOL2),
 238                         .ENAWREN(A1EN),
 239                         .REGCEA(|1),
 240                         .RSTA(|0),
 241                         .WEAWEL(2'b0),
 242
 243                         .DIBDI(DI),
 244                         .DIPBDIP(DIP),
 245                         .DOBDO(DOBDO),
 246                         .DOPBDOP(DOPBDOP),
 247                         .ADDRBRDADDR(B1ADDR_13),
 248                         .CLKBRDCLK(CLK3 ^ !CLKPOL3),
 249                         .ENBRDEN(|1),
 250                         .REGCEBREGCE(|0),
 251                         .RSTBRST(|0),
 252                         .WEBWEU(B1EN_2)
 253                 );
 254         end endgenerate
 255 endmodule