Merge pull request #1406 from whitequark/connect_rpc
[yosys.git] / techlibs / xilinx / xc7_brams.txt
1
2 bram $__XILINX_RAMB36_SDP
3 init 1
4 abits 9
5 dbits 72
6 groups 2
7 ports 1 1
8 wrmode 0 1
9 enable 1 8
10 transp 0 0
11 clocks 2 3
12 clkpol 2 3
13 endbram
14
15 bram $__XILINX_RAMB18_SDP
16 init 1
17 abits 9
18 dbits 36
19 groups 2
20 ports 1 1
21 wrmode 0 1
22 enable 1 4
23 transp 0 0
24 clocks 2 3
25 clkpol 2 3
26 endbram
27
28 bram $__XILINX_RAMB36_TDP
29 init 1
30 abits 10 @a10d36
31 dbits 36 @a10d36
32 abits 11 @a11d18
33 dbits 18 @a11d18
34 abits 12 @a12d9
35 dbits 9 @a12d9
36 abits 13 @a13d4
37 dbits 4 @a13d4
38 abits 14 @a14d2
39 dbits 2 @a14d2
40 abits 15 @a15d1
41 dbits 1 @a15d1
42 groups 2
43 ports 1 1
44 wrmode 0 1
45 enable 1 4 @a10d36
46 enable 1 2 @a11d18
47 enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1
48 transp 0 0
49 clocks 2 3
50 clkpol 2 3
51 endbram
52
53 bram $__XILINX_RAMB18_TDP
54 init 1
55 abits 10 @a10d18
56 dbits 18 @a10d18
57 abits 11 @a11d9
58 dbits 9 @a11d9
59 abits 12 @a12d4
60 dbits 4 @a12d4
61 abits 13 @a13d2
62 dbits 2 @a13d2
63 abits 14 @a14d1
64 dbits 1 @a14d1
65 groups 2
66 ports 1 1
67 wrmode 0 1
68 enable 1 2 @a10d18
69 enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
70 transp 0 0
71 clocks 2 3
72 clkpol 2 3
73 endbram
74
75 match $__XILINX_RAMB36_SDP
76 min bits 4096
77 min efficiency 5
78 shuffle_enable B
79 make_transp
80 or_next_if_better
81 endmatch
82
83 match $__XILINX_RAMB18_SDP
84 min bits 4096
85 min efficiency 5
86 shuffle_enable B
87 make_transp
88 or_next_if_better
89 endmatch
90
91 match $__XILINX_RAMB36_TDP
92 min bits 4096
93 min efficiency 5
94 shuffle_enable B
95 make_transp
96 or_next_if_better
97 endmatch
98
99 match $__XILINX_RAMB18_TDP
100 min bits 4096
101 min efficiency 5
102 shuffle_enable B
103 make_transp
104 endmatch
105