techlibs/xilinx/xc7_brams_map.v

   1 module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
   2         parameter CLKPOL2 = 1;
   3         parameter CLKPOL3 = 1;
   4         parameter [36863:0] INIT = 36864'bx;
   5
   6         input CLK2;
   7         input CLK3;
   8
   9         input [8:0] A1ADDR;
  10         output [71:0] A1DATA;
  11         input A1EN;
  12
  13         input [8:0] B1ADDR;
  14         input [71:0] B1DATA;
  15         input [7:0] B1EN;
  16
  17         wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
  18         wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
  19
  20         wire [7:0] DIP, DOP;
  21         wire [63:0] DI, DO;
  22
  23         assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
  24                           DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
  25
  26         assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
  27                  DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
  28
  29         RAMB36E1 #(
  30                 .RAM_MODE("SDP"),
  31                 .READ_WIDTH_A(72),
  32                 .WRITE_WIDTH_B(72),
  33                 .WRITE_MODE_A("READ_FIRST"),
  34                 .WRITE_MODE_B("READ_FIRST"),
  35                 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
  36                 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
  37                 `include "brams_init_36.vh"
  38                 .SIM_DEVICE("7SERIES")
  39         ) _TECHMAP_REPLACE_ (
  40                 .DOBDO(DO[63:32]),
  41                 .DOADO(DO[31:0]),
  42                 .DOPBDOP(DOP[7:4]),
  43                 .DOPADOP(DOP[3:0]),
  44                 .DIBDI(DI[63:32]),
  45                 .DIADI(DI[31:0]),
  46                 .DIPBDIP(DIP[7:4]),
  47                 .DIPADIP(DIP[3:0]),
  48
  49                 .ADDRARDADDR(A1ADDR_16),
  50                 .CLKARDCLK(CLK2),
  51                 .ENARDEN(A1EN),
  52                 .REGCEAREGCE(|1),
  53                 .RSTRAMARSTRAM(|0),
  54                 .RSTREGARSTREG(|0),
  55                 .WEA(4'b0),
  56
  57                 .ADDRBWRADDR(B1ADDR_16),
  58                 .CLKBWRCLK(CLK3),
  59                 .ENBWREN(|1),
  60                 .REGCEB(|0),
  61                 .RSTRAMB(|0),
  62                 .RSTREGB(|0),
  63                 .WEBWE(B1EN)
  64         );
  65 endmodule
  66
  67 // ------------------------------------------------------------------------
  68
  69 module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
  70         parameter CLKPOL2 = 1;
  71         parameter CLKPOL3 = 1;
  72         parameter [18431:0] INIT = 18432'bx;
  73
  74         input CLK2;
  75         input CLK3;
  76
  77         input [8:0] A1ADDR;
  78         output [35:0] A1DATA;
  79         input A1EN;
  80
  81         input [8:0] B1ADDR;
  82         input [35:0] B1DATA;
  83         input [3:0] B1EN;
  84
  85         wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
  86         wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
  87
  88         wire [3:0] DIP, DOP;
  89         wire [31:0] DI, DO;
  90
  91         assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
  92         assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
  93
  94         RAMB18E1 #(
  95                 .RAM_MODE("SDP"),
  96                 .READ_WIDTH_A(36),
  97                 .WRITE_WIDTH_B(36),
  98                 .WRITE_MODE_A("READ_FIRST"),
  99                 .WRITE_MODE_B("READ_FIRST"),
 100                 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 101                 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 102                 `include "brams_init_18.vh"
 103                 .SIM_DEVICE("7SERIES")
 104         ) _TECHMAP_REPLACE_ (
 105                 .DOBDO(DO[31:16]),
 106                 .DOADO(DO[15:0]),
 107                 .DOPBDOP(DOP[3:2]),
 108                 .DOPADOP(DOP[1:0]),
 109                 .DIBDI(DI[31:16]),
 110                 .DIADI(DI[15:0]),
 111                 .DIPBDIP(DIP[3:2]),
 112                 .DIPADIP(DIP[1:0]),
 113
 114                 .ADDRARDADDR(A1ADDR_14),
 115                 .CLKARDCLK(CLK2),
 116                 .ENARDEN(A1EN),
 117                 .REGCEAREGCE(|1),
 118                 .RSTRAMARSTRAM(|0),
 119                 .RSTREGARSTREG(|0),
 120                 .WEA(2'b0),
 121
 122                 .ADDRBWRADDR(B1ADDR_14),
 123                 .CLKBWRCLK(CLK3),
 124                 .ENBWREN(|1),
 125                 .REGCEB(|0),
 126                 .RSTRAMB(|0),
 127                 .RSTREGB(|0),
 128                 .WEBWE(B1EN)
 129         );
 130 endmodule
 131
 132 // ------------------------------------------------------------------------
 133
 134 module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 135         parameter CFG_ABITS = 10;
 136         parameter CFG_DBITS = 36;
 137         parameter CFG_ENABLE_B = 4;
 138
 139         parameter CLKPOL2 = 1;
 140         parameter CLKPOL3 = 1;
 141         parameter [36863:0] INIT = 36864'bx;
 142
 143         input CLK2;
 144         input CLK3;
 145
 146         input [CFG_ABITS-1:0] A1ADDR;
 147         output [CFG_DBITS-1:0] A1DATA;
 148         input A1EN;
 149
 150         input [CFG_ABITS-1:0] B1ADDR;
 151         input [CFG_DBITS-1:0] B1DATA;
 152         input [CFG_ENABLE_B-1:0] B1EN;
 153
 154         wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
 155         wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
 156         wire [7:0] B1EN_8 = B1EN;
 157
 158         wire [3:0] DIP, DOP;
 159         wire [31:0] DI, DO;
 160
 161         wire [31:0] DOBDO;
 162         wire [3:0] DOPBDOP;
 163
 164         assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
 165         assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
 166
 167         generate if (CFG_DBITS > 8) begin
 168                 RAMB36E1 #(
 169                         .RAM_MODE("TDP"),
 170                         .READ_WIDTH_A(CFG_DBITS),
 171                         .READ_WIDTH_B(CFG_DBITS),
 172                         .WRITE_WIDTH_A(CFG_DBITS),
 173                         .WRITE_WIDTH_B(CFG_DBITS),
 174                         .WRITE_MODE_A("READ_FIRST"),
 175                         .WRITE_MODE_B("READ_FIRST"),
 176                         .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 177                         .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 178                         `include "brams_init_36.vh"
 179                         .SIM_DEVICE("7SERIES")
 180                 ) _TECHMAP_REPLACE_ (
 181                         .DIADI(32'd0),
 182                         .DIPADIP(4'd0),
 183                         .DOADO(DO[31:0]),
 184                         .DOPADOP(DOP[3:0]),
 185                         .ADDRARDADDR(A1ADDR_16),
 186                         .CLKARDCLK(CLK2),
 187                         .ENARDEN(A1EN),
 188                         .REGCEAREGCE(|1),
 189                         .RSTRAMARSTRAM(|0),
 190                         .RSTREGARSTREG(|0),
 191                         .WEA(4'b0),
 192
 193                         .DIBDI(DI),
 194                         .DIPBDIP(DIP),
 195                         .DOBDO(DOBDO),
 196                         .DOPBDOP(DOPBDOP),
 197                         .ADDRBWRADDR(B1ADDR_16),
 198                         .CLKBWRCLK(CLK3),
 199                         .ENBWREN(|1),
 200                         .REGCEB(|0),
 201                         .RSTRAMB(|0),
 202                         .RSTREGB(|0),
 203                         .WEBWE(B1EN_8)
 204                 );
 205         end else begin
 206                 RAMB36E1 #(
 207                         .RAM_MODE("TDP"),
 208                         .READ_WIDTH_A(CFG_DBITS),
 209                         .READ_WIDTH_B(CFG_DBITS),
 210                         .WRITE_WIDTH_A(CFG_DBITS),
 211                         .WRITE_WIDTH_B(CFG_DBITS),
 212                         .WRITE_MODE_A("READ_FIRST"),
 213                         .WRITE_MODE_B("READ_FIRST"),
 214                         .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 215                         .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 216                         `include "brams_init_32.vh"
 217                         .SIM_DEVICE("7SERIES")
 218                 ) _TECHMAP_REPLACE_ (
 219                         .DIADI(32'd0),
 220                         .DIPADIP(4'd0),
 221                         .DOADO(DO[31:0]),
 222                         .DOPADOP(DOP[3:0]),
 223                         .ADDRARDADDR(A1ADDR_16),
 224                         .CLKARDCLK(CLK2),
 225                         .ENARDEN(A1EN),
 226                         .REGCEAREGCE(|1),
 227                         .RSTRAMARSTRAM(|0),
 228                         .RSTREGARSTREG(|0),
 229                         .WEA(4'b0),
 230
 231                         .DIBDI(DI),
 232                         .DIPBDIP(DIP),
 233                         .DOBDO(DOBDO),
 234                         .DOPBDOP(DOPBDOP),
 235                         .ADDRBWRADDR(B1ADDR_16),
 236                         .CLKBWRCLK(CLK3),
 237                         .ENBWREN(|1),
 238                         .REGCEB(|0),
 239                         .RSTRAMB(|0),
 240                         .RSTREGB(|0),
 241                         .WEBWE(B1EN_8)
 242                 );
 243         end endgenerate
 244 endmodule
 245
 246 // ------------------------------------------------------------------------
 247
 248 module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 249         parameter CFG_ABITS = 10;
 250         parameter CFG_DBITS = 18;
 251         parameter CFG_ENABLE_B = 2;
 252
 253         parameter CLKPOL2 = 1;
 254         parameter CLKPOL3 = 1;
 255         parameter [18431:0] INIT = 18432'bx;
 256
 257         input CLK2;
 258         input CLK3;
 259
 260         input [CFG_ABITS-1:0] A1ADDR;
 261         output [CFG_DBITS-1:0] A1DATA;
 262         input A1EN;
 263
 264         input [CFG_ABITS-1:0] B1ADDR;
 265         input [CFG_DBITS-1:0] B1DATA;
 266         input [CFG_ENABLE_B-1:0] B1EN;
 267
 268         wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
 269         wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
 270         wire [3:0] B1EN_4 = B1EN;
 271
 272         wire [1:0] DIP, DOP;
 273         wire [15:0] DI, DO;
 274
 275         wire [15:0] DOBDO;
 276         wire [1:0] DOPBDOP;
 277
 278         assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
 279         assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
 280
 281         generate if (CFG_DBITS > 8) begin
 282                 RAMB18E1 #(
 283                         .RAM_MODE("TDP"),
 284                         .READ_WIDTH_A(CFG_DBITS),
 285                         .READ_WIDTH_B(CFG_DBITS),
 286                         .WRITE_WIDTH_A(CFG_DBITS),
 287                         .WRITE_WIDTH_B(CFG_DBITS),
 288                         .WRITE_MODE_A("READ_FIRST"),
 289                         .WRITE_MODE_B("READ_FIRST"),
 290                         .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 291                         .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 292                         `include "brams_init_18.vh"
 293                         .SIM_DEVICE("7SERIES")
 294                 ) _TECHMAP_REPLACE_ (
 295                         .DIADI(16'b0),
 296                         .DIPADIP(2'b0),
 297                         .DOADO(DO),
 298                         .DOPADOP(DOP),
 299                         .ADDRARDADDR(A1ADDR_14),
 300                         .CLKARDCLK(CLK2),
 301                         .ENARDEN(A1EN),
 302                         .REGCEAREGCE(|1),
 303                         .RSTRAMARSTRAM(|0),
 304                         .RSTREGARSTREG(|0),
 305                         .WEA(2'b0),
 306
 307                         .DIBDI(DI),
 308                         .DIPBDIP(DIP),
 309                         .DOBDO(DOBDO),
 310                         .DOPBDOP(DOPBDOP),
 311                         .ADDRBWRADDR(B1ADDR_14),
 312                         .CLKBWRCLK(CLK3),
 313                         .ENBWREN(|1),
 314                         .REGCEB(|0),
 315                         .RSTRAMB(|0),
 316                         .RSTREGB(|0),
 317                         .WEBWE(B1EN_4)
 318                 );
 319         end else begin
 320                 RAMB18E1 #(
 321                         .RAM_MODE("TDP"),
 322                         .READ_WIDTH_A(CFG_DBITS),
 323                         .READ_WIDTH_B(CFG_DBITS),
 324                         .WRITE_WIDTH_A(CFG_DBITS),
 325                         .WRITE_WIDTH_B(CFG_DBITS),
 326                         .WRITE_MODE_A("READ_FIRST"),
 327                         .WRITE_MODE_B("READ_FIRST"),
 328                         .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 329                         .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 330                         `include "brams_init_16.vh"
 331                         .SIM_DEVICE("7SERIES")
 332                 ) _TECHMAP_REPLACE_ (
 333                         .DIADI(16'b0),
 334                         .DIPADIP(2'b0),
 335                         .DOADO(DO),
 336                         .DOPADOP(DOP),
 337                         .ADDRARDADDR(A1ADDR_14),
 338                         .CLKARDCLK(CLK2),
 339                         .ENARDEN(A1EN),
 340                         .REGCEAREGCE(|1),
 341                         .RSTRAMARSTRAM(|0),
 342                         .RSTREGARSTREG(|0),
 343                         .WEA(2'b0),
 344
 345                         .DIBDI(DI),
 346                         .DIPBDIP(DIP),
 347                         .DOBDO(DOBDO),
 348                         .DOPBDOP(DOPBDOP),
 349                         .ADDRBWRADDR(B1ADDR_14),
 350                         .CLKBWRCLK(CLK3),
 351                         .ENBWREN(|1),
 352                         .REGCEB(|0),
 353                         .RSTRAMB(|0),
 354                         .RSTREGB(|0),
 355                         .WEBWE(B1EN_4)
 356                 );
 357         end endgenerate
 358 endmodule
 359