1 module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
4 parameter [36863:0] INIT = 36864'bx;
17 wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
18 wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
23 assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
24 DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
26 assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
27 DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
33 .WRITE_MODE_A("READ_FIRST"),
34 .WRITE_MODE_B("READ_FIRST"),
35 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
36 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
37 `include "brams_init_36.vh"
38 .SIM_DEVICE("7SERIES")
49 .ADDRARDADDR(A1ADDR_16),
57 .ADDRBWRADDR(B1ADDR_16),
67 // ------------------------------------------------------------------------
69 module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
70 parameter CLKPOL2 = 1;
71 parameter CLKPOL3 = 1;
72 parameter [18431:0] INIT = 18432'bx;
85 wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
86 wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
91 assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
92 assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
98 .WRITE_MODE_A("READ_FIRST"),
99 .WRITE_MODE_B("READ_FIRST"),
100 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
101 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
102 `include "brams_init_18.vh"
103 .SIM_DEVICE("7SERIES")
104 ) _TECHMAP_REPLACE_ (
114 .ADDRARDADDR(A1ADDR_14),
122 .ADDRBWRADDR(B1ADDR_14),
132 // ------------------------------------------------------------------------
134 module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
135 parameter CFG_ABITS = 10;
136 parameter CFG_DBITS = 36;
137 parameter CFG_ENABLE_B = 4;
139 parameter CLKPOL2 = 1;
140 parameter CLKPOL3 = 1;
141 parameter [36863:0] INIT = 36864'bx;
146 input [CFG_ABITS-1:0] A1ADDR;
147 output [CFG_DBITS-1:0] A1DATA;
150 input [CFG_ABITS-1:0] B1ADDR;
151 input [CFG_DBITS-1:0] B1DATA;
152 input [CFG_ENABLE_B-1:0] B1EN;
154 wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
155 wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
156 wire [7:0] B1EN_8 = B1EN;
164 assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
165 assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
167 generate if (CFG_DBITS > 8) begin
170 .READ_WIDTH_A(CFG_DBITS),
171 .READ_WIDTH_B(CFG_DBITS),
172 .WRITE_WIDTH_A(CFG_DBITS),
173 .WRITE_WIDTH_B(CFG_DBITS),
174 .WRITE_MODE_A("READ_FIRST"),
175 .WRITE_MODE_B("READ_FIRST"),
176 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
177 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
178 `include "brams_init_36.vh"
179 .SIM_DEVICE("7SERIES")
180 ) _TECHMAP_REPLACE_ (
185 .ADDRARDADDR(A1ADDR_16),
197 .ADDRBWRADDR(B1ADDR_16),
208 .READ_WIDTH_A(CFG_DBITS),
209 .READ_WIDTH_B(CFG_DBITS),
210 .WRITE_WIDTH_A(CFG_DBITS),
211 .WRITE_WIDTH_B(CFG_DBITS),
212 .WRITE_MODE_A("READ_FIRST"),
213 .WRITE_MODE_B("READ_FIRST"),
214 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
215 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
216 `include "brams_init_32.vh"
217 .SIM_DEVICE("7SERIES")
218 ) _TECHMAP_REPLACE_ (
223 .ADDRARDADDR(A1ADDR_16),
235 .ADDRBWRADDR(B1ADDR_16),
246 // ------------------------------------------------------------------------
248 module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
249 parameter CFG_ABITS = 10;
250 parameter CFG_DBITS = 18;
251 parameter CFG_ENABLE_B = 2;
253 parameter CLKPOL2 = 1;
254 parameter CLKPOL3 = 1;
255 parameter [18431:0] INIT = 18432'bx;
260 input [CFG_ABITS-1:0] A1ADDR;
261 output [CFG_DBITS-1:0] A1DATA;
264 input [CFG_ABITS-1:0] B1ADDR;
265 input [CFG_DBITS-1:0] B1DATA;
266 input [CFG_ENABLE_B-1:0] B1EN;
268 wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
269 wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
270 wire [3:0] B1EN_4 = B1EN;
278 assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
279 assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
281 generate if (CFG_DBITS > 8) begin
284 .READ_WIDTH_A(CFG_DBITS),
285 .READ_WIDTH_B(CFG_DBITS),
286 .WRITE_WIDTH_A(CFG_DBITS),
287 .WRITE_WIDTH_B(CFG_DBITS),
288 .WRITE_MODE_A("READ_FIRST"),
289 .WRITE_MODE_B("READ_FIRST"),
290 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
291 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
292 `include "brams_init_18.vh"
293 .SIM_DEVICE("7SERIES")
294 ) _TECHMAP_REPLACE_ (
299 .ADDRARDADDR(A1ADDR_14),
311 .ADDRBWRADDR(B1ADDR_14),
322 .READ_WIDTH_A(CFG_DBITS),
323 .READ_WIDTH_B(CFG_DBITS),
324 .WRITE_WIDTH_A(CFG_DBITS),
325 .WRITE_WIDTH_B(CFG_DBITS),
326 .WRITE_MODE_A("READ_FIRST"),
327 .WRITE_MODE_B("READ_FIRST"),
328 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
329 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
330 `include "brams_init_16.vh"
331 .SIM_DEVICE("7SERIES")
332 ) _TECHMAP_REPLACE_ (
337 .ADDRARDADDR(A1ADDR_14),
349 .ADDRBWRADDR(B1ADDR_14),