techlibs/xilinx/xc7_cells_xtra.v

   1 // Created by cells_xtra.py from Xilinx models
   2
   3 module GTHE2_CHANNEL (...);
   4     parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
   5     parameter [0:0] ACJTAG_MODE = 1'b0;
   6     parameter [0:0] ACJTAG_RESET = 1'b0;
   7     parameter [19:0] ADAPT_CFG0 = 20'h00C10;
   8     parameter ALIGN_COMMA_DOUBLE = "FALSE";
   9     parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
  10     parameter integer ALIGN_COMMA_WORD = 1;
  11     parameter ALIGN_MCOMMA_DET = "TRUE";
  12     parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
  13     parameter ALIGN_PCOMMA_DET = "TRUE";
  14     parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
  15     parameter [0:0] A_RXOSCALRESET = 1'b0;
  16     parameter CBCC_DATA_SOURCE_SEL = "DECODED";
  17     parameter [41:0] CFOK_CFG = 42'h24800040E80;
  18     parameter [5:0] CFOK_CFG2 = 6'b100000;
  19     parameter [5:0] CFOK_CFG3 = 6'b100000;
  20     parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
  21     parameter integer CHAN_BOND_MAX_SKEW = 7;
  22     parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
  23     parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
  24     parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
  25     parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
  26     parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
  27     parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
  28     parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
  29     parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
  30     parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
  31     parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
  32     parameter CHAN_BOND_SEQ_2_USE = "FALSE";
  33     parameter integer CHAN_BOND_SEQ_LEN = 1;
  34     parameter CLK_CORRECT_USE = "TRUE";
  35     parameter CLK_COR_KEEP_IDLE = "FALSE";
  36     parameter integer CLK_COR_MAX_LAT = 20;
  37     parameter integer CLK_COR_MIN_LAT = 18;
  38     parameter CLK_COR_PRECEDENCE = "TRUE";
  39     parameter integer CLK_COR_REPEAT_WAIT = 0;
  40     parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
  41     parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
  42     parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
  43     parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
  44     parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
  45     parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
  46     parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
  47     parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
  48     parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
  49     parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
  50     parameter CLK_COR_SEQ_2_USE = "FALSE";
  51     parameter integer CLK_COR_SEQ_LEN = 1;
  52     parameter [28:0] CPLL_CFG = 29'h00BC07DC;
  53     parameter integer CPLL_FBDIV = 4;
  54     parameter integer CPLL_FBDIV_45 = 5;
  55     parameter [23:0] CPLL_INIT_CFG = 24'h00001E;
  56     parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
  57     parameter integer CPLL_REFCLK_DIV = 1;
  58     parameter DEC_MCOMMA_DETECT = "TRUE";
  59     parameter DEC_PCOMMA_DETECT = "TRUE";
  60     parameter DEC_VALID_COMMA_ONLY = "TRUE";
  61     parameter [23:0] DMONITOR_CFG = 24'h000A00;
  62     parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
  63     parameter [5:0] ES_CONTROL = 6'b000000;
  64     parameter ES_ERRDET_EN = "FALSE";
  65     parameter ES_EYE_SCAN_EN = "TRUE";
  66     parameter [11:0] ES_HORZ_OFFSET = 12'h000;
  67     parameter [9:0] ES_PMA_CFG = 10'b0000000000;
  68     parameter [4:0] ES_PRESCALE = 5'b00000;
  69     parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
  70     parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
  71     parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
  72     parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
  73     parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
  74     parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
  75     parameter FTS_LANE_DESKEW_EN = "FALSE";
  76     parameter [2:0] GEARBOX_MODE = 3'b000;
  77     parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
  78     parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
  79     parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0;
  80     parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
  81     parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
  82     parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
  83     parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
  84     parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
  85     parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
  86     parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
  87     parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
  88     parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
  89     parameter [0:0] LOOPBACK_CFG = 1'b0;
  90     parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
  91     parameter PCS_PCIE_EN = "FALSE";
  92     parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
  93     parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
  94     parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
  95     parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
  96     parameter [31:0] PMA_RSV = 32'b00000000000000000000000010000000;
  97     parameter [31:0] PMA_RSV2 = 32'b00011100000000000000000000001010;
  98     parameter [1:0] PMA_RSV3 = 2'b00;
  99     parameter [14:0] PMA_RSV4 = 15'b000000000001000;
 100     parameter [3:0] PMA_RSV5 = 4'b0000;
 101     parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
 102     parameter [4:0] RXBUFRESET_TIME = 5'b00001;
 103     parameter RXBUF_ADDR_MODE = "FULL";
 104     parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
 105     parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
 106     parameter RXBUF_EN = "TRUE";
 107     parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
 108     parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
 109     parameter RXBUF_RESET_ON_EIDLE = "FALSE";
 110     parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
 111     parameter integer RXBUF_THRESH_OVFLW = 61;
 112     parameter RXBUF_THRESH_OVRD = "FALSE";
 113     parameter integer RXBUF_THRESH_UNDFLW = 4;
 114     parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
 115     parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
 116     parameter [82:0] RXCDR_CFG = 83'h0002007FE2000C208001A;
 117     parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
 118     parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
 119     parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
 120     parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
 121     parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
 122     parameter [15:0] RXDLY_CFG = 16'h001F;
 123     parameter [8:0] RXDLY_LCFG = 9'h030;
 124     parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
 125     parameter RXGEARBOX_EN = "FALSE";
 126     parameter [4:0] RXISCANRESET_TIME = 5'b00001;
 127     parameter [13:0] RXLPM_HF_CFG = 14'b00001000000000;
 128     parameter [17:0] RXLPM_LF_CFG = 18'b001001000000000000;
 129     parameter [6:0] RXOOB_CFG = 7'b0000110;
 130     parameter RXOOB_CLK_CFG = "PMA";
 131     parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
 132     parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
 133     parameter integer RXOUT_DIV = 2;
 134     parameter [4:0] RXPCSRESET_TIME = 5'b00001;
 135     parameter [23:0] RXPHDLY_CFG = 24'h084020;
 136     parameter [23:0] RXPH_CFG = 24'hC00002;
 137     parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
 138     parameter [1:0] RXPI_CFG0 = 2'b00;
 139     parameter [1:0] RXPI_CFG1 = 2'b00;
 140     parameter [1:0] RXPI_CFG2 = 2'b00;
 141     parameter [1:0] RXPI_CFG3 = 2'b00;
 142     parameter [0:0] RXPI_CFG4 = 1'b0;
 143     parameter [0:0] RXPI_CFG5 = 1'b0;
 144     parameter [2:0] RXPI_CFG6 = 3'b100;
 145     parameter [4:0] RXPMARESET_TIME = 5'b00011;
 146     parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
 147     parameter integer RXSLIDE_AUTO_WAIT = 7;
 148     parameter RXSLIDE_MODE = "OFF";
 149     parameter [0:0] RXSYNC_MULTILANE = 1'b0;
 150     parameter [0:0] RXSYNC_OVRD = 1'b0;
 151     parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
 152     parameter [23:0] RX_BIAS_CFG = 24'b000011000000000000010000;
 153     parameter [5:0] RX_BUFFER_CFG = 6'b000000;
 154     parameter integer RX_CLK25_DIV = 7;
 155     parameter [0:0] RX_CLKMUX_PD = 1'b1;
 156     parameter [1:0] RX_CM_SEL = 2'b11;
 157     parameter [3:0] RX_CM_TRIM = 4'b0100;
 158     parameter integer RX_DATA_WIDTH = 20;
 159     parameter [5:0] RX_DDI_SEL = 6'b000000;
 160     parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
 161     parameter RX_DEFER_RESET_BUF_EN = "TRUE";
 162     parameter [3:0] RX_DFELPM_CFG0 = 4'b0110;
 163     parameter [0:0] RX_DFELPM_CFG1 = 1'b0;
 164     parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
 165     parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
 166     parameter [2:0] RX_DFE_AGC_CFG1 = 3'b010;
 167     parameter [3:0] RX_DFE_AGC_CFG2 = 4'b0000;
 168     parameter [0:0] RX_DFE_AGC_OVRDEN = 1'b1;
 169     parameter [22:0] RX_DFE_GAIN_CFG = 23'h0020C0;
 170     parameter [11:0] RX_DFE_H2_CFG = 12'b000000000000;
 171     parameter [11:0] RX_DFE_H3_CFG = 12'b000001000000;
 172     parameter [10:0] RX_DFE_H4_CFG = 11'b00011100000;
 173     parameter [10:0] RX_DFE_H5_CFG = 11'b00011100000;
 174     parameter [10:0] RX_DFE_H6_CFG = 11'b00000100000;
 175     parameter [10:0] RX_DFE_H7_CFG = 11'b00000100000;
 176     parameter [32:0] RX_DFE_KL_CFG = 33'b000000000000000000000001100010000;
 177     parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01;
 178     parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010;
 179     parameter [3:0] RX_DFE_KL_LPM_KH_CFG2 = 4'b0010;
 180     parameter [0:0] RX_DFE_KL_LPM_KH_OVRDEN = 1'b1;
 181     parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b10;
 182     parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010;
 183     parameter [3:0] RX_DFE_KL_LPM_KL_CFG2 = 4'b0010;
 184     parameter [0:0] RX_DFE_KL_LPM_KL_OVRDEN = 1'b1;
 185     parameter [15:0] RX_DFE_LPM_CFG = 16'h0080;
 186     parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
 187     parameter [53:0] RX_DFE_ST_CFG = 54'h00E100000C003F;
 188     parameter [16:0] RX_DFE_UT_CFG = 17'b00011100000000000;
 189     parameter [16:0] RX_DFE_VP_CFG = 17'b00011101010100011;
 190     parameter RX_DISPERR_SEQ_MATCH = "TRUE";
 191     parameter integer RX_INT_DATAWIDTH = 0;
 192     parameter [12:0] RX_OS_CFG = 13'b0000010000000;
 193     parameter integer RX_SIG_VALID_DLY = 10;
 194     parameter RX_XCLK_SEL = "RXREC";
 195     parameter integer SAS_MAX_COM = 64;
 196     parameter integer SAS_MIN_COM = 36;
 197     parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
 198     parameter [2:0] SATA_BURST_VAL = 3'b100;
 199     parameter SATA_CPLL_CFG = "VCO_3000MHZ";
 200     parameter [2:0] SATA_EIDLE_VAL = 3'b100;
 201     parameter integer SATA_MAX_BURST = 8;
 202     parameter integer SATA_MAX_INIT = 21;
 203     parameter integer SATA_MAX_WAKE = 7;
 204     parameter integer SATA_MIN_BURST = 4;
 205     parameter integer SATA_MIN_INIT = 12;
 206     parameter integer SATA_MIN_WAKE = 4;
 207     parameter SHOW_REALIGN_COMMA = "TRUE";
 208     parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001;
 209     parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
 210     parameter SIM_RESET_SPEEDUP = "TRUE";
 211     parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
 212     parameter SIM_VERSION = "1.1";
 213     parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
 214     parameter [2:0] TERM_RCAL_OVRD = 3'b000;
 215     parameter [7:0] TRANS_TIME_RATE = 8'h0E;
 216     parameter [31:0] TST_RSV = 32'h00000000;
 217     parameter TXBUF_EN = "TRUE";
 218     parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
 219     parameter [15:0] TXDLY_CFG = 16'h001F;
 220     parameter [8:0] TXDLY_LCFG = 9'h030;
 221     parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
 222     parameter TXGEARBOX_EN = "FALSE";
 223     parameter [0:0] TXOOB_CFG = 1'b0;
 224     parameter integer TXOUT_DIV = 2;
 225     parameter [4:0] TXPCSRESET_TIME = 5'b00001;
 226     parameter [23:0] TXPHDLY_CFG = 24'h084020;
 227     parameter [15:0] TXPH_CFG = 16'h0780;
 228     parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
 229     parameter [1:0] TXPI_CFG0 = 2'b00;
 230     parameter [1:0] TXPI_CFG1 = 2'b00;
 231     parameter [1:0] TXPI_CFG2 = 2'b00;
 232     parameter [0:0] TXPI_CFG3 = 1'b0;
 233     parameter [0:0] TXPI_CFG4 = 1'b0;
 234     parameter [2:0] TXPI_CFG5 = 3'b100;
 235     parameter [0:0] TXPI_GREY_SEL = 1'b0;
 236     parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
 237     parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
 238     parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
 239     parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
 240     parameter [4:0] TXPMARESET_TIME = 5'b00001;
 241     parameter [0:0] TXSYNC_MULTILANE = 1'b0;
 242     parameter [0:0] TXSYNC_OVRD = 1'b0;
 243     parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
 244     parameter integer TX_CLK25_DIV = 7;
 245     parameter [0:0] TX_CLKMUX_PD = 1'b1;
 246     parameter integer TX_DATA_WIDTH = 20;
 247     parameter [5:0] TX_DEEMPH0 = 6'b000000;
 248     parameter [5:0] TX_DEEMPH1 = 6'b000000;
 249     parameter TX_DRIVE_MODE = "DIRECT";
 250     parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
 251     parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
 252     parameter integer TX_INT_DATAWIDTH = 0;
 253     parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
 254     parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
 255     parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
 256     parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
 257     parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
 258     parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
 259     parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
 260     parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
 261     parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
 262     parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
 263     parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
 264     parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
 265     parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
 266     parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
 267     parameter [16:0] TX_RXDETECT_PRECHARGE_TIME = 17'h00000;
 268     parameter [2:0] TX_RXDETECT_REF = 3'b100;
 269     parameter TX_XCLK_SEL = "TXUSR";
 270     parameter [0:0] UCODEER_CLR = 1'b0;
 271     parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
 272     output CPLLFBCLKLOST;
 273     output CPLLLOCK;
 274     output CPLLREFCLKLOST;
 275     output DRPRDY;
 276     output EYESCANDATAERROR;
 277     output GTHTXN;
 278     output GTHTXP;
 279     output GTREFCLKMONITOR;
 280     output PHYSTATUS;
 281     output RSOSINTDONE;
 282     output RXBYTEISALIGNED;
 283     output RXBYTEREALIGN;
 284     output RXCDRLOCK;
 285     output RXCHANBONDSEQ;
 286     output RXCHANISALIGNED;
 287     output RXCHANREALIGN;
 288     output RXCOMINITDET;
 289     output RXCOMMADET;
 290     output RXCOMSASDET;
 291     output RXCOMWAKEDET;
 292     output RXDFESLIDETAPSTARTED;
 293     output RXDFESLIDETAPSTROBEDONE;
 294     output RXDFESLIDETAPSTROBESTARTED;
 295     output RXDFESTADAPTDONE;
 296     output RXDLYSRESETDONE;
 297     output RXELECIDLE;
 298     output RXOSINTSTARTED;
 299     output RXOSINTSTROBEDONE;
 300     output RXOSINTSTROBESTARTED;
 301     output RXOUTCLK;
 302     output RXOUTCLKFABRIC;
 303     output RXOUTCLKPCS;
 304     output RXPHALIGNDONE;
 305     output RXPMARESETDONE;
 306     output RXPRBSERR;
 307     output RXQPISENN;
 308     output RXQPISENP;
 309     output RXRATEDONE;
 310     output RXRESETDONE;
 311     output RXSYNCDONE;
 312     output RXSYNCOUT;
 313     output RXVALID;
 314     output TXCOMFINISH;
 315     output TXDLYSRESETDONE;
 316     output TXGEARBOXREADY;
 317     output TXOUTCLK;
 318     output TXOUTCLKFABRIC;
 319     output TXOUTCLKPCS;
 320     output TXPHALIGNDONE;
 321     output TXPHINITDONE;
 322     output TXPMARESETDONE;
 323     output TXQPISENN;
 324     output TXQPISENP;
 325     output TXRATEDONE;
 326     output TXRESETDONE;
 327     output TXSYNCDONE;
 328     output TXSYNCOUT;
 329     output [14:0] DMONITOROUT;
 330     output [15:0] DRPDO;
 331     output [15:0] PCSRSVDOUT;
 332     output [1:0] RXCLKCORCNT;
 333     output [1:0] RXDATAVALID;
 334     output [1:0] RXHEADERVALID;
 335     output [1:0] RXSTARTOFSEQ;
 336     output [1:0] TXBUFSTATUS;
 337     output [2:0] RXBUFSTATUS;
 338     output [2:0] RXSTATUS;
 339     output [4:0] RXCHBONDO;
 340     output [4:0] RXPHMONITOR;
 341     output [4:0] RXPHSLIPMONITOR;
 342     output [5:0] RXHEADER;
 343     output [63:0] RXDATA;
 344     output [6:0] RXMONITOROUT;
 345     output [7:0] RXCHARISCOMMA;
 346     output [7:0] RXCHARISK;
 347     output [7:0] RXDISPERR;
 348     output [7:0] RXNOTINTABLE;
 349     input CFGRESET;
 350     (* invertible_pin = "IS_CLKRSVD0_INVERTED" *)
 351     input CLKRSVD0;
 352     (* invertible_pin = "IS_CLKRSVD1_INVERTED" *)
 353     input CLKRSVD1;
 354     (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *)
 355     input CPLLLOCKDETCLK;
 356     input CPLLLOCKEN;
 357     input CPLLPD;
 358     input CPLLRESET;
 359     input DMONFIFORESET;
 360     (* invertible_pin = "IS_DMONITORCLK_INVERTED" *)
 361     input DMONITORCLK;
 362     (* invertible_pin = "IS_DRPCLK_INVERTED" *)
 363     input DRPCLK;
 364     input DRPEN;
 365     input DRPWE;
 366     input EYESCANMODE;
 367     input EYESCANRESET;
 368     input EYESCANTRIGGER;
 369     (* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
 370     input GTGREFCLK;
 371     input GTHRXN;
 372     input GTHRXP;
 373     input GTNORTHREFCLK0;
 374     input GTNORTHREFCLK1;
 375     input GTREFCLK0;
 376     input GTREFCLK1;
 377     input GTRESETSEL;
 378     input GTRXRESET;
 379     input GTSOUTHREFCLK0;
 380     input GTSOUTHREFCLK1;
 381     input GTTXRESET;
 382     input QPLLCLK;
 383     input QPLLREFCLK;
 384     input RESETOVRD;
 385     input RX8B10BEN;
 386     input RXBUFRESET;
 387     input RXCDRFREQRESET;
 388     input RXCDRHOLD;
 389     input RXCDROVRDEN;
 390     input RXCDRRESET;
 391     input RXCDRRESETRSV;
 392     input RXCHBONDEN;
 393     input RXCHBONDMASTER;
 394     input RXCHBONDSLAVE;
 395     input RXCOMMADETEN;
 396     input RXDDIEN;
 397     input RXDFEAGCHOLD;
 398     input RXDFEAGCOVRDEN;
 399     input RXDFECM1EN;
 400     input RXDFELFHOLD;
 401     input RXDFELFOVRDEN;
 402     input RXDFELPMRESET;
 403     input RXDFESLIDETAPADAPTEN;
 404     input RXDFESLIDETAPHOLD;
 405     input RXDFESLIDETAPINITOVRDEN;
 406     input RXDFESLIDETAPONLYADAPTEN;
 407     input RXDFESLIDETAPOVRDEN;
 408     input RXDFESLIDETAPSTROBE;
 409     input RXDFETAP2HOLD;
 410     input RXDFETAP2OVRDEN;
 411     input RXDFETAP3HOLD;
 412     input RXDFETAP3OVRDEN;
 413     input RXDFETAP4HOLD;
 414     input RXDFETAP4OVRDEN;
 415     input RXDFETAP5HOLD;
 416     input RXDFETAP5OVRDEN;
 417     input RXDFETAP6HOLD;
 418     input RXDFETAP6OVRDEN;
 419     input RXDFETAP7HOLD;
 420     input RXDFETAP7OVRDEN;
 421     input RXDFEUTHOLD;
 422     input RXDFEUTOVRDEN;
 423     input RXDFEVPHOLD;
 424     input RXDFEVPOVRDEN;
 425     input RXDFEVSEN;
 426     input RXDFEXYDEN;
 427     input RXDLYBYPASS;
 428     input RXDLYEN;
 429     input RXDLYOVRDEN;
 430     input RXDLYSRESET;
 431     input RXGEARBOXSLIP;
 432     input RXLPMEN;
 433     input RXLPMHFHOLD;
 434     input RXLPMHFOVRDEN;
 435     input RXLPMLFHOLD;
 436     input RXLPMLFKLOVRDEN;
 437     input RXMCOMMAALIGNEN;
 438     input RXOOBRESET;
 439     input RXOSCALRESET;
 440     input RXOSHOLD;
 441     input RXOSINTEN;
 442     input RXOSINTHOLD;
 443     input RXOSINTNTRLEN;
 444     input RXOSINTOVRDEN;
 445     input RXOSINTSTROBE;
 446     input RXOSINTTESTOVRDEN;
 447     input RXOSOVRDEN;
 448     input RXPCOMMAALIGNEN;
 449     input RXPCSRESET;
 450     input RXPHALIGN;
 451     input RXPHALIGNEN;
 452     input RXPHDLYPD;
 453     input RXPHDLYRESET;
 454     input RXPHOVRDEN;
 455     input RXPMARESET;
 456     input RXPOLARITY;
 457     input RXPRBSCNTRESET;
 458     input RXQPIEN;
 459     input RXRATEMODE;
 460     input RXSLIDE;
 461     input RXSYNCALLIN;
 462     input RXSYNCIN;
 463     input RXSYNCMODE;
 464     input RXUSERRDY;
 465     (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
 466     input RXUSRCLK2;
 467     (* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
 468     input RXUSRCLK;
 469     input SETERRSTATUS;
 470     (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *)
 471     input SIGVALIDCLK;
 472     input TX8B10BEN;
 473     input TXCOMINIT;
 474     input TXCOMSAS;
 475     input TXCOMWAKE;
 476     input TXDEEMPH;
 477     input TXDETECTRX;
 478     input TXDIFFPD;
 479     input TXDLYBYPASS;
 480     input TXDLYEN;
 481     input TXDLYHOLD;
 482     input TXDLYOVRDEN;
 483     input TXDLYSRESET;
 484     input TXDLYUPDOWN;
 485     input TXELECIDLE;
 486     input TXINHIBIT;
 487     input TXPCSRESET;
 488     input TXPDELECIDLEMODE;
 489     input TXPHALIGN;
 490     input TXPHALIGNEN;
 491     input TXPHDLYPD;
 492     input TXPHDLYRESET;
 493     (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
 494     input TXPHDLYTSTCLK;
 495     input TXPHINIT;
 496     input TXPHOVRDEN;
 497     input TXPIPPMEN;
 498     input TXPIPPMOVRDEN;
 499     input TXPIPPMPD;
 500     input TXPIPPMSEL;
 501     input TXPISOPD;
 502     input TXPMARESET;
 503     input TXPOLARITY;
 504     input TXPOSTCURSORINV;
 505     input TXPRBSFORCEERR;
 506     input TXPRECURSORINV;
 507     input TXQPIBIASEN;
 508     input TXQPISTRONGPDOWN;
 509     input TXQPIWEAKPUP;
 510     input TXRATEMODE;
 511     input TXSTARTSEQ;
 512     input TXSWING;
 513     input TXSYNCALLIN;
 514     input TXSYNCIN;
 515     input TXSYNCMODE;
 516     input TXUSERRDY;
 517     (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
 518     input TXUSRCLK2;
 519     (* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
 520     input TXUSRCLK;
 521     input [13:0] RXADAPTSELTEST;
 522     input [15:0] DRPDI;
 523     input [15:0] GTRSVD;
 524     input [15:0] PCSRSVDIN;
 525     input [19:0] TSTIN;
 526     input [1:0] RXELECIDLEMODE;
 527     input [1:0] RXMONITORSEL;
 528     input [1:0] RXPD;
 529     input [1:0] RXSYSCLKSEL;
 530     input [1:0] TXPD;
 531     input [1:0] TXSYSCLKSEL;
 532     input [2:0] CPLLREFCLKSEL;
 533     input [2:0] LOOPBACK;
 534     input [2:0] RXCHBONDLEVEL;
 535     input [2:0] RXOUTCLKSEL;
 536     input [2:0] RXPRBSSEL;
 537     input [2:0] RXRATE;
 538     input [2:0] TXBUFDIFFCTRL;
 539     input [2:0] TXHEADER;
 540     input [2:0] TXMARGIN;
 541     input [2:0] TXOUTCLKSEL;
 542     input [2:0] TXPRBSSEL;
 543     input [2:0] TXRATE;
 544     input [3:0] RXOSINTCFG;
 545     input [3:0] RXOSINTID0;
 546     input [3:0] TXDIFFCTRL;
 547     input [4:0] PCSRSVDIN2;
 548     input [4:0] PMARSVDIN;
 549     input [4:0] RXCHBONDI;
 550     input [4:0] RXDFEAGCTRL;
 551     input [4:0] RXDFESLIDETAP;
 552     input [4:0] TXPIPPMSTEPSIZE;
 553     input [4:0] TXPOSTCURSOR;
 554     input [4:0] TXPRECURSOR;
 555     input [5:0] RXDFESLIDETAPID;
 556     input [63:0] TXDATA;
 557     input [6:0] TXMAINCURSOR;
 558     input [6:0] TXSEQUENCE;
 559     input [7:0] TX8B10BBYPASS;
 560     input [7:0] TXCHARDISPMODE;
 561     input [7:0] TXCHARDISPVAL;
 562     input [7:0] TXCHARISK;
 563     input [8:0] DRPADDR;
 564 endmodule
 565
 566 module GTHE2_COMMON (...);
 567     parameter [63:0] BIAS_CFG = 64'h0000040000001000;
 568     parameter [31:0] COMMON_CFG = 32'h0000001C;
 569     parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
 570     parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
 571     parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0;
 572     parameter [26:0] QPLL_CFG = 27'h0480181;
 573     parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000;
 574     parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000;
 575     parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0;
 576     parameter [9:0] QPLL_CP = 10'b0000011111;
 577     parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0;
 578     parameter [0:0] QPLL_DMONITOR_SEL = 1'b0;
 579     parameter [9:0] QPLL_FBDIV = 10'b0000000000;
 580     parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0;
 581     parameter [0:0] QPLL_FBDIV_RATIO = 1'b0;
 582     parameter [23:0] QPLL_INIT_CFG = 24'h000006;
 583     parameter [15:0] QPLL_LOCK_CFG = 16'h01E8;
 584     parameter [3:0] QPLL_LPF = 4'b1111;
 585     parameter integer QPLL_REFCLK_DIV = 2;
 586     parameter [0:0] QPLL_RP_COMP = 1'b0;
 587     parameter [1:0] QPLL_VTRL_RESET = 2'b00;
 588     parameter [1:0] RCAL_CFG = 2'b00;
 589     parameter [15:0] RSVD_ATTR0 = 16'h0000;
 590     parameter [15:0] RSVD_ATTR1 = 16'h0000;
 591     parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001;
 592     parameter SIM_RESET_SPEEDUP = "TRUE";
 593     parameter SIM_VERSION = "1.1";
 594     output DRPRDY;
 595     output QPLLFBCLKLOST;
 596     output QPLLLOCK;
 597     output QPLLOUTCLK;
 598     output QPLLOUTREFCLK;
 599     output QPLLREFCLKLOST;
 600     output REFCLKOUTMONITOR;
 601     output [15:0] DRPDO;
 602     output [15:0] PMARSVDOUT;
 603     output [7:0] QPLLDMONITOR;
 604     input BGBYPASSB;
 605     input BGMONITORENB;
 606     input BGPDB;
 607     input BGRCALOVRDENB;
 608     (* invertible_pin = "IS_DRPCLK_INVERTED" *)
 609     input DRPCLK;
 610     input DRPEN;
 611     input DRPWE;
 612     (* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
 613     input GTGREFCLK;
 614     input GTNORTHREFCLK0;
 615     input GTNORTHREFCLK1;
 616     input GTREFCLK0;
 617     input GTREFCLK1;
 618     input GTSOUTHREFCLK0;
 619     input GTSOUTHREFCLK1;
 620     (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *)
 621     input QPLLLOCKDETCLK;
 622     input QPLLLOCKEN;
 623     input QPLLOUTRESET;
 624     input QPLLPD;
 625     input QPLLRESET;
 626     input RCALENB;
 627     input [15:0] DRPDI;
 628     input [15:0] QPLLRSVD1;
 629     input [2:0] QPLLREFCLKSEL;
 630     input [4:0] BGRCALOVRD;
 631     input [4:0] QPLLRSVD2;
 632     input [7:0] DRPADDR;
 633     input [7:0] PMARSVD;
 634 endmodule
 635
 636 module GTPE2_CHANNEL (...);
 637     parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
 638     parameter [0:0] ACJTAG_MODE = 1'b0;
 639     parameter [0:0] ACJTAG_RESET = 1'b0;
 640     parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000;
 641     parameter ALIGN_COMMA_DOUBLE = "FALSE";
 642     parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
 643     parameter integer ALIGN_COMMA_WORD = 1;
 644     parameter ALIGN_MCOMMA_DET = "TRUE";
 645     parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
 646     parameter ALIGN_PCOMMA_DET = "TRUE";
 647     parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
 648     parameter CBCC_DATA_SOURCE_SEL = "DECODED";
 649     parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000;
 650     parameter [6:0] CFOK_CFG2 = 7'b0100000;
 651     parameter [6:0] CFOK_CFG3 = 7'b0100000;
 652     parameter [0:0] CFOK_CFG4 = 1'b0;
 653     parameter [1:0] CFOK_CFG5 = 2'b00;
 654     parameter [3:0] CFOK_CFG6 = 4'b0000;
 655     parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
 656     parameter integer CHAN_BOND_MAX_SKEW = 7;
 657     parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
 658     parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
 659     parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
 660     parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
 661     parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
 662     parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
 663     parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
 664     parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
 665     parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
 666     parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
 667     parameter CHAN_BOND_SEQ_2_USE = "FALSE";
 668     parameter integer CHAN_BOND_SEQ_LEN = 1;
 669     parameter [0:0] CLK_COMMON_SWING = 1'b0;
 670     parameter CLK_CORRECT_USE = "TRUE";
 671     parameter CLK_COR_KEEP_IDLE = "FALSE";
 672     parameter integer CLK_COR_MAX_LAT = 20;
 673     parameter integer CLK_COR_MIN_LAT = 18;
 674     parameter CLK_COR_PRECEDENCE = "TRUE";
 675     parameter integer CLK_COR_REPEAT_WAIT = 0;
 676     parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
 677     parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
 678     parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
 679     parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
 680     parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
 681     parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
 682     parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
 683     parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
 684     parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
 685     parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
 686     parameter CLK_COR_SEQ_2_USE = "FALSE";
 687     parameter integer CLK_COR_SEQ_LEN = 1;
 688     parameter DEC_MCOMMA_DETECT = "TRUE";
 689     parameter DEC_PCOMMA_DETECT = "TRUE";
 690     parameter DEC_VALID_COMMA_ONLY = "TRUE";
 691     parameter [23:0] DMONITOR_CFG = 24'h000A00;
 692     parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
 693     parameter [5:0] ES_CONTROL = 6'b000000;
 694     parameter ES_ERRDET_EN = "FALSE";
 695     parameter ES_EYE_SCAN_EN = "FALSE";
 696     parameter [11:0] ES_HORZ_OFFSET = 12'h010;
 697     parameter [9:0] ES_PMA_CFG = 10'b0000000000;
 698     parameter [4:0] ES_PRESCALE = 5'b00000;
 699     parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
 700     parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
 701     parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
 702     parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
 703     parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
 704     parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
 705     parameter FTS_LANE_DESKEW_EN = "FALSE";
 706     parameter [2:0] GEARBOX_MODE = 3'b000;
 707     parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
 708     parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
 709     parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
 710     parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
 711     parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
 712     parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
 713     parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
 714     parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
 715     parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
 716     parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
 717     parameter [0:0] LOOPBACK_CFG = 1'b0;
 718     parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
 719     parameter PCS_PCIE_EN = "FALSE";
 720     parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
 721     parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
 722     parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
 723     parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
 724     parameter [0:0] PMA_LOOPBACK_CFG = 1'b0;
 725     parameter [31:0] PMA_RSV = 32'h00000333;
 726     parameter [31:0] PMA_RSV2 = 32'h00002050;
 727     parameter [1:0] PMA_RSV3 = 2'b00;
 728     parameter [3:0] PMA_RSV4 = 4'b0000;
 729     parameter [0:0] PMA_RSV5 = 1'b0;
 730     parameter [0:0] PMA_RSV6 = 1'b0;
 731     parameter [0:0] PMA_RSV7 = 1'b0;
 732     parameter [4:0] RXBUFRESET_TIME = 5'b00001;
 733     parameter RXBUF_ADDR_MODE = "FULL";
 734     parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
 735     parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
 736     parameter RXBUF_EN = "TRUE";
 737     parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
 738     parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
 739     parameter RXBUF_RESET_ON_EIDLE = "FALSE";
 740     parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
 741     parameter integer RXBUF_THRESH_OVFLW = 61;
 742     parameter RXBUF_THRESH_OVRD = "FALSE";
 743     parameter integer RXBUF_THRESH_UNDFLW = 4;
 744     parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
 745     parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
 746     parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010;
 747     parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
 748     parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
 749     parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
 750     parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
 751     parameter [15:0] RXDLY_CFG = 16'h0010;
 752     parameter [8:0] RXDLY_LCFG = 9'h020;
 753     parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
 754     parameter RXGEARBOX_EN = "FALSE";
 755     parameter [4:0] RXISCANRESET_TIME = 5'b00001;
 756     parameter [6:0] RXLPMRESET_TIME = 7'b0001111;
 757     parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0;
 758     parameter [3:0] RXLPM_CFG = 4'b0110;
 759     parameter [0:0] RXLPM_CFG1 = 1'b0;
 760     parameter [0:0] RXLPM_CM_CFG = 1'b0;
 761     parameter [8:0] RXLPM_GC_CFG = 9'b111100010;
 762     parameter [2:0] RXLPM_GC_CFG2 = 3'b001;
 763     parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000;
 764     parameter [4:0] RXLPM_HF_CFG2 = 5'b01010;
 765     parameter [3:0] RXLPM_HF_CFG3 = 4'b0000;
 766     parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0;
 767     parameter [0:0] RXLPM_INCM_CFG = 1'b0;
 768     parameter [0:0] RXLPM_IPCM_CFG = 1'b0;
 769     parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000;
 770     parameter [4:0] RXLPM_LF_CFG2 = 5'b01010;
 771     parameter [2:0] RXLPM_OSINT_CFG = 3'b100;
 772     parameter [6:0] RXOOB_CFG = 7'b0000110;
 773     parameter RXOOB_CLK_CFG = "PMA";
 774     parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
 775     parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
 776     parameter integer RXOUT_DIV = 2;
 777     parameter [4:0] RXPCSRESET_TIME = 5'b00001;
 778     parameter [23:0] RXPHDLY_CFG = 24'h084000;
 779     parameter [23:0] RXPH_CFG = 24'hC00002;
 780     parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
 781     parameter [2:0] RXPI_CFG0 = 3'b000;
 782     parameter [0:0] RXPI_CFG1 = 1'b0;
 783     parameter [0:0] RXPI_CFG2 = 1'b0;
 784     parameter [4:0] RXPMARESET_TIME = 5'b00011;
 785     parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
 786     parameter integer RXSLIDE_AUTO_WAIT = 7;
 787     parameter RXSLIDE_MODE = "OFF";
 788     parameter [0:0] RXSYNC_MULTILANE = 1'b0;
 789     parameter [0:0] RXSYNC_OVRD = 1'b0;
 790     parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
 791     parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011;
 792     parameter [5:0] RX_BUFFER_CFG = 6'b000000;
 793     parameter integer RX_CLK25_DIV = 7;
 794     parameter [0:0] RX_CLKMUX_EN = 1'b1;
 795     parameter [1:0] RX_CM_SEL = 2'b11;
 796     parameter [3:0] RX_CM_TRIM = 4'b0100;
 797     parameter integer RX_DATA_WIDTH = 20;
 798     parameter [5:0] RX_DDI_SEL = 6'b000000;
 799     parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
 800     parameter RX_DEFER_RESET_BUF_EN = "TRUE";
 801     parameter RX_DISPERR_SEQ_MATCH = "TRUE";
 802     parameter [12:0] RX_OS_CFG = 13'b0001111110000;
 803     parameter integer RX_SIG_VALID_DLY = 10;
 804     parameter RX_XCLK_SEL = "RXREC";
 805     parameter integer SAS_MAX_COM = 64;
 806     parameter integer SAS_MIN_COM = 36;
 807     parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
 808     parameter [2:0] SATA_BURST_VAL = 3'b100;
 809     parameter [2:0] SATA_EIDLE_VAL = 3'b100;
 810     parameter integer SATA_MAX_BURST = 8;
 811     parameter integer SATA_MAX_INIT = 21;
 812     parameter integer SATA_MAX_WAKE = 7;
 813     parameter integer SATA_MIN_BURST = 4;
 814     parameter integer SATA_MIN_INIT = 12;
 815     parameter integer SATA_MIN_WAKE = 4;
 816     parameter SATA_PLL_CFG = "VCO_3000MHZ";
 817     parameter SHOW_REALIGN_COMMA = "TRUE";
 818     parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
 819     parameter SIM_RESET_SPEEDUP = "TRUE";
 820     parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
 821     parameter SIM_VERSION = "1.0";
 822     parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
 823     parameter [2:0] TERM_RCAL_OVRD = 3'b000;
 824     parameter [7:0] TRANS_TIME_RATE = 8'h0E;
 825     parameter [31:0] TST_RSV = 32'h00000000;
 826     parameter TXBUF_EN = "TRUE";
 827     parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
 828     parameter [15:0] TXDLY_CFG = 16'h0010;
 829     parameter [8:0] TXDLY_LCFG = 9'h020;
 830     parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
 831     parameter TXGEARBOX_EN = "FALSE";
 832     parameter [0:0] TXOOB_CFG = 1'b0;
 833     parameter integer TXOUT_DIV = 2;
 834     parameter [4:0] TXPCSRESET_TIME = 5'b00001;
 835     parameter [23:0] TXPHDLY_CFG = 24'h084000;
 836     parameter [15:0] TXPH_CFG = 16'h0400;
 837     parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
 838     parameter [1:0] TXPI_CFG0 = 2'b00;
 839     parameter [1:0] TXPI_CFG1 = 2'b00;
 840     parameter [1:0] TXPI_CFG2 = 2'b00;
 841     parameter [0:0] TXPI_CFG3 = 1'b0;
 842     parameter [0:0] TXPI_CFG4 = 1'b0;
 843     parameter [2:0] TXPI_CFG5 = 3'b000;
 844     parameter [0:0] TXPI_GREY_SEL = 1'b0;
 845     parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
 846     parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
 847     parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
 848     parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
 849     parameter [4:0] TXPMARESET_TIME = 5'b00001;
 850     parameter [0:0] TXSYNC_MULTILANE = 1'b0;
 851     parameter [0:0] TXSYNC_OVRD = 1'b0;
 852     parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
 853     parameter integer TX_CLK25_DIV = 7;
 854     parameter [0:0] TX_CLKMUX_EN = 1'b1;
 855     parameter integer TX_DATA_WIDTH = 20;
 856     parameter [5:0] TX_DEEMPH0 = 6'b000000;
 857     parameter [5:0] TX_DEEMPH1 = 6'b000000;
 858     parameter TX_DRIVE_MODE = "DIRECT";
 859     parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
 860     parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
 861     parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
 862     parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
 863     parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
 864     parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
 865     parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
 866     parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
 867     parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
 868     parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
 869     parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
 870     parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
 871     parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
 872     parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
 873     parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
 874     parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
 875     parameter [2:0] TX_RXDETECT_REF = 3'b100;
 876     parameter TX_XCLK_SEL = "TXUSR";
 877     parameter [0:0] UCODEER_CLR = 1'b0;
 878     parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
 879     output DRPRDY;
 880     output EYESCANDATAERROR;
 881     output GTPTXN;
 882     output GTPTXP;
 883     output PHYSTATUS;
 884     output PMARSVDOUT0;
 885     output PMARSVDOUT1;
 886     output RXBYTEISALIGNED;
 887     output RXBYTEREALIGN;
 888     output RXCDRLOCK;
 889     output RXCHANBONDSEQ;
 890     output RXCHANISALIGNED;
 891     output RXCHANREALIGN;
 892     output RXCOMINITDET;
 893     output RXCOMMADET;
 894     output RXCOMSASDET;
 895     output RXCOMWAKEDET;
 896     output RXDLYSRESETDONE;
 897     output RXELECIDLE;
 898     output RXHEADERVALID;
 899     output RXOSINTDONE;
 900     output RXOSINTSTARTED;
 901     output RXOSINTSTROBEDONE;
 902     output RXOSINTSTROBESTARTED;
 903     output RXOUTCLK;
 904     output RXOUTCLKFABRIC;
 905     output RXOUTCLKPCS;
 906     output RXPHALIGNDONE;
 907     output RXPMARESETDONE;
 908     output RXPRBSERR;
 909     output RXRATEDONE;
 910     output RXRESETDONE;
 911     output RXSYNCDONE;
 912     output RXSYNCOUT;
 913     output RXVALID;
 914     output TXCOMFINISH;
 915     output TXDLYSRESETDONE;
 916     output TXGEARBOXREADY;
 917     output TXOUTCLK;
 918     output TXOUTCLKFABRIC;
 919     output TXOUTCLKPCS;
 920     output TXPHALIGNDONE;
 921     output TXPHINITDONE;
 922     output TXPMARESETDONE;
 923     output TXRATEDONE;
 924     output TXRESETDONE;
 925     output TXSYNCDONE;
 926     output TXSYNCOUT;
 927     output [14:0] DMONITOROUT;
 928     output [15:0] DRPDO;
 929     output [15:0] PCSRSVDOUT;
 930     output [1:0] RXCLKCORCNT;
 931     output [1:0] RXDATAVALID;
 932     output [1:0] RXSTARTOFSEQ;
 933     output [1:0] TXBUFSTATUS;
 934     output [2:0] RXBUFSTATUS;
 935     output [2:0] RXHEADER;
 936     output [2:0] RXSTATUS;
 937     output [31:0] RXDATA;
 938     output [3:0] RXCHARISCOMMA;
 939     output [3:0] RXCHARISK;
 940     output [3:0] RXCHBONDO;
 941     output [3:0] RXDISPERR;
 942     output [3:0] RXNOTINTABLE;
 943     output [4:0] RXPHMONITOR;
 944     output [4:0] RXPHSLIPMONITOR;
 945     input CFGRESET;
 946     (* invertible_pin = "IS_CLKRSVD0_INVERTED" *)
 947     input CLKRSVD0;
 948     (* invertible_pin = "IS_CLKRSVD1_INVERTED" *)
 949     input CLKRSVD1;
 950     input DMONFIFORESET;
 951     (* invertible_pin = "IS_DMONITORCLK_INVERTED" *)
 952     input DMONITORCLK;
 953     (* invertible_pin = "IS_DRPCLK_INVERTED" *)
 954     input DRPCLK;
 955     input DRPEN;
 956     input DRPWE;
 957     input EYESCANMODE;
 958     input EYESCANRESET;
 959     input EYESCANTRIGGER;
 960     input GTPRXN;
 961     input GTPRXP;
 962     input GTRESETSEL;
 963     input GTRXRESET;
 964     input GTTXRESET;
 965     input PLL0CLK;
 966     input PLL0REFCLK;
 967     input PLL1CLK;
 968     input PLL1REFCLK;
 969     input PMARSVDIN0;
 970     input PMARSVDIN1;
 971     input PMARSVDIN2;
 972     input PMARSVDIN3;
 973     input PMARSVDIN4;
 974     input RESETOVRD;
 975     input RX8B10BEN;
 976     input RXBUFRESET;
 977     input RXCDRFREQRESET;
 978     input RXCDRHOLD;
 979     input RXCDROVRDEN;
 980     input RXCDRRESET;
 981     input RXCDRRESETRSV;
 982     input RXCHBONDEN;
 983     input RXCHBONDMASTER;
 984     input RXCHBONDSLAVE;
 985     input RXCOMMADETEN;
 986     input RXDDIEN;
 987     input RXDFEXYDEN;
 988     input RXDLYBYPASS;
 989     input RXDLYEN;
 990     input RXDLYOVRDEN;
 991     input RXDLYSRESET;
 992     input RXGEARBOXSLIP;
 993     input RXLPMHFHOLD;
 994     input RXLPMHFOVRDEN;
 995     input RXLPMLFHOLD;
 996     input RXLPMLFOVRDEN;
 997     input RXLPMOSINTNTRLEN;
 998     input RXLPMRESET;
 999     input RXMCOMMAALIGNEN;
1000     input RXOOBRESET;
1001     input RXOSCALRESET;
1002     input RXOSHOLD;
1003     input RXOSINTEN;
1004     input RXOSINTHOLD;
1005     input RXOSINTNTRLEN;
1006     input RXOSINTOVRDEN;
1007     input RXOSINTPD;
1008     input RXOSINTSTROBE;
1009     input RXOSINTTESTOVRDEN;
1010     input RXOSOVRDEN;
1011     input RXPCOMMAALIGNEN;
1012     input RXPCSRESET;
1013     input RXPHALIGN;
1014     input RXPHALIGNEN;
1015     input RXPHDLYPD;
1016     input RXPHDLYRESET;
1017     input RXPHOVRDEN;
1018     input RXPMARESET;
1019     input RXPOLARITY;
1020     input RXPRBSCNTRESET;
1021     input RXRATEMODE;
1022     input RXSLIDE;
1023     input RXSYNCALLIN;
1024     input RXSYNCIN;
1025     input RXSYNCMODE;
1026     input RXUSERRDY;
1027     (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
1028     input RXUSRCLK2;
1029     (* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
1030     input RXUSRCLK;
1031     input SETERRSTATUS;
1032     (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *)
1033     input SIGVALIDCLK;
1034     input TX8B10BEN;
1035     input TXCOMINIT;
1036     input TXCOMSAS;
1037     input TXCOMWAKE;
1038     input TXDEEMPH;
1039     input TXDETECTRX;
1040     input TXDIFFPD;
1041     input TXDLYBYPASS;
1042     input TXDLYEN;
1043     input TXDLYHOLD;
1044     input TXDLYOVRDEN;
1045     input TXDLYSRESET;
1046     input TXDLYUPDOWN;
1047     input TXELECIDLE;
1048     input TXINHIBIT;
1049     input TXPCSRESET;
1050     input TXPDELECIDLEMODE;
1051     input TXPHALIGN;
1052     input TXPHALIGNEN;
1053     input TXPHDLYPD;
1054     input TXPHDLYRESET;
1055     (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
1056     input TXPHDLYTSTCLK;
1057     input TXPHINIT;
1058     input TXPHOVRDEN;
1059     input TXPIPPMEN;
1060     input TXPIPPMOVRDEN;
1061     input TXPIPPMPD;
1062     input TXPIPPMSEL;
1063     input TXPISOPD;
1064     input TXPMARESET;
1065     input TXPOLARITY;
1066     input TXPOSTCURSORINV;
1067     input TXPRBSFORCEERR;
1068     input TXPRECURSORINV;
1069     input TXRATEMODE;
1070     input TXSTARTSEQ;
1071     input TXSWING;
1072     input TXSYNCALLIN;
1073     input TXSYNCIN;
1074     input TXSYNCMODE;
1075     input TXUSERRDY;
1076     (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
1077     input TXUSRCLK2;
1078     (* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
1079     input TXUSRCLK;
1080     input [13:0] RXADAPTSELTEST;
1081     input [15:0] DRPDI;
1082     input [15:0] GTRSVD;
1083     input [15:0] PCSRSVDIN;
1084     input [19:0] TSTIN;
1085     input [1:0] RXELECIDLEMODE;
1086     input [1:0] RXPD;
1087     input [1:0] RXSYSCLKSEL;
1088     input [1:0] TXPD;
1089     input [1:0] TXSYSCLKSEL;
1090     input [2:0] LOOPBACK;
1091     input [2:0] RXCHBONDLEVEL;
1092     input [2:0] RXOUTCLKSEL;
1093     input [2:0] RXPRBSSEL;
1094     input [2:0] RXRATE;
1095     input [2:0] TXBUFDIFFCTRL;
1096     input [2:0] TXHEADER;
1097     input [2:0] TXMARGIN;
1098     input [2:0] TXOUTCLKSEL;
1099     input [2:0] TXPRBSSEL;
1100     input [2:0] TXRATE;
1101     input [31:0] TXDATA;
1102     input [3:0] RXCHBONDI;
1103     input [3:0] RXOSINTCFG;
1104     input [3:0] RXOSINTID0;
1105     input [3:0] TX8B10BBYPASS;
1106     input [3:0] TXCHARDISPMODE;
1107     input [3:0] TXCHARDISPVAL;
1108     input [3:0] TXCHARISK;
1109     input [3:0] TXDIFFCTRL;
1110     input [4:0] TXPIPPMSTEPSIZE;
1111     input [4:0] TXPOSTCURSOR;
1112     input [4:0] TXPRECURSOR;
1113     input [6:0] TXMAINCURSOR;
1114     input [6:0] TXSEQUENCE;
1115     input [8:0] DRPADDR;
1116 endmodule
1117
1118 module GTPE2_COMMON (...);
1119     parameter [63:0] BIAS_CFG = 64'h0000000000000000;
1120     parameter [31:0] COMMON_CFG = 32'h00000000;
1121     parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
1122     parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0;
1123     parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0;
1124     parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0;
1125     parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0;
1126     parameter [26:0] PLL0_CFG = 27'h01F03DC;
1127     parameter [0:0] PLL0_DMON_CFG = 1'b0;
1128     parameter integer PLL0_FBDIV = 4;
1129     parameter integer PLL0_FBDIV_45 = 5;
1130     parameter [23:0] PLL0_INIT_CFG = 24'h00001E;
1131     parameter [8:0] PLL0_LOCK_CFG = 9'h1E8;
1132     parameter integer PLL0_REFCLK_DIV = 1;
1133     parameter [26:0] PLL1_CFG = 27'h01F03DC;
1134     parameter [0:0] PLL1_DMON_CFG = 1'b0;
1135     parameter integer PLL1_FBDIV = 4;
1136     parameter integer PLL1_FBDIV_45 = 5;
1137     parameter [23:0] PLL1_INIT_CFG = 24'h00001E;
1138     parameter [8:0] PLL1_LOCK_CFG = 9'h1E8;
1139     parameter integer PLL1_REFCLK_DIV = 1;
1140     parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000;
1141     parameter [15:0] RSVD_ATTR0 = 16'h0000;
1142     parameter [15:0] RSVD_ATTR1 = 16'h0000;
1143     parameter [2:0] SIM_PLL0REFCLK_SEL = 3'b001;
1144     parameter [2:0] SIM_PLL1REFCLK_SEL = 3'b001;
1145     parameter SIM_RESET_SPEEDUP = "TRUE";
1146     parameter SIM_VERSION = "1.0";
1147     output DRPRDY;
1148     output PLL0FBCLKLOST;
1149     output PLL0LOCK;
1150     output PLL0OUTCLK;
1151     output PLL0OUTREFCLK;
1152     output PLL0REFCLKLOST;
1153     output PLL1FBCLKLOST;
1154     output PLL1LOCK;
1155     output PLL1OUTCLK;
1156     output PLL1OUTREFCLK;
1157     output PLL1REFCLKLOST;
1158     output REFCLKOUTMONITOR0;
1159     output REFCLKOUTMONITOR1;
1160     output [15:0] DRPDO;
1161     output [15:0] PMARSVDOUT;
1162     output [7:0] DMONITOROUT;
1163     input BGBYPASSB;
1164     input BGMONITORENB;
1165     input BGPDB;
1166     input BGRCALOVRDENB;
1167     (* invertible_pin = "IS_DRPCLK_INVERTED" *)
1168     input DRPCLK;
1169     input DRPEN;
1170     input DRPWE;
1171     input GTEASTREFCLK0;
1172     input GTEASTREFCLK1;
1173     (* invertible_pin = "IS_GTGREFCLK0_INVERTED" *)
1174     input GTGREFCLK0;
1175     (* invertible_pin = "IS_GTGREFCLK1_INVERTED" *)
1176     input GTGREFCLK1;
1177     input GTREFCLK0;
1178     input GTREFCLK1;
1179     input GTWESTREFCLK0;
1180     input GTWESTREFCLK1;
1181     (* invertible_pin = "IS_PLL0LOCKDETCLK_INVERTED" *)
1182     input PLL0LOCKDETCLK;
1183     input PLL0LOCKEN;
1184     input PLL0PD;
1185     input PLL0RESET;
1186     (* invertible_pin = "IS_PLL1LOCKDETCLK_INVERTED" *)
1187     input PLL1LOCKDETCLK;
1188     input PLL1LOCKEN;
1189     input PLL1PD;
1190     input PLL1RESET;
1191     input RCALENB;
1192     input [15:0] DRPDI;
1193     input [15:0] PLLRSVD1;
1194     input [2:0] PLL0REFCLKSEL;
1195     input [2:0] PLL1REFCLKSEL;
1196     input [4:0] BGRCALOVRD;
1197     input [4:0] PLLRSVD2;
1198     input [7:0] DRPADDR;
1199     input [7:0] PMARSVD;
1200 endmodule
1201
1202 module GTXE2_CHANNEL (...);
1203     parameter ALIGN_COMMA_DOUBLE = "FALSE";
1204     parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
1205     parameter integer ALIGN_COMMA_WORD = 1;
1206     parameter ALIGN_MCOMMA_DET = "TRUE";
1207     parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
1208     parameter ALIGN_PCOMMA_DET = "TRUE";
1209     parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
1210     parameter CBCC_DATA_SOURCE_SEL = "DECODED";
1211     parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
1212     parameter integer CHAN_BOND_MAX_SKEW = 7;
1213     parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
1214     parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
1215     parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
1216     parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
1217     parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
1218     parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
1219     parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
1220     parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
1221     parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
1222     parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
1223     parameter CHAN_BOND_SEQ_2_USE = "FALSE";
1224     parameter integer CHAN_BOND_SEQ_LEN = 1;
1225     parameter CLK_CORRECT_USE = "TRUE";
1226     parameter CLK_COR_KEEP_IDLE = "FALSE";
1227     parameter integer CLK_COR_MAX_LAT = 20;
1228     parameter integer CLK_COR_MIN_LAT = 18;
1229     parameter CLK_COR_PRECEDENCE = "TRUE";
1230     parameter integer CLK_COR_REPEAT_WAIT = 0;
1231     parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
1232     parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
1233     parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
1234     parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
1235     parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
1236     parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
1237     parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
1238     parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
1239     parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
1240     parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
1241     parameter CLK_COR_SEQ_2_USE = "FALSE";
1242     parameter integer CLK_COR_SEQ_LEN = 1;
1243     parameter [23:0] CPLL_CFG = 24'hB007D8;
1244     parameter integer CPLL_FBDIV = 4;
1245     parameter integer CPLL_FBDIV_45 = 5;
1246     parameter [23:0] CPLL_INIT_CFG = 24'h00001E;
1247     parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
1248     parameter integer CPLL_REFCLK_DIV = 1;
1249     parameter DEC_MCOMMA_DETECT = "TRUE";
1250     parameter DEC_PCOMMA_DETECT = "TRUE";
1251     parameter DEC_VALID_COMMA_ONLY = "TRUE";
1252     parameter [23:0] DMONITOR_CFG = 24'h000A00;
1253     parameter [5:0] ES_CONTROL = 6'b000000;
1254     parameter ES_ERRDET_EN = "FALSE";
1255     parameter ES_EYE_SCAN_EN = "FALSE";
1256     parameter [11:0] ES_HORZ_OFFSET = 12'h000;
1257     parameter [9:0] ES_PMA_CFG = 10'b0000000000;
1258     parameter [4:0] ES_PRESCALE = 5'b00000;
1259     parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
1260     parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
1261     parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
1262     parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
1263     parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
1264     parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
1265     parameter FTS_LANE_DESKEW_EN = "FALSE";
1266     parameter [2:0] GEARBOX_MODE = 3'b000;
1267     parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0;
1268     parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
1269     parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
1270     parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
1271     parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
1272     parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
1273     parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
1274     parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
1275     parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
1276     parameter PCS_PCIE_EN = "FALSE";
1277     parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
1278     parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
1279     parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
1280     parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
1281     parameter [31:0] PMA_RSV = 32'h00000000;
1282     parameter [15:0] PMA_RSV2 = 16'h2050;
1283     parameter [1:0] PMA_RSV3 = 2'b00;
1284     parameter [31:0] PMA_RSV4 = 32'h00000000;
1285     parameter [4:0] RXBUFRESET_TIME = 5'b00001;
1286     parameter RXBUF_ADDR_MODE = "FULL";
1287     parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
1288     parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
1289     parameter RXBUF_EN = "TRUE";
1290     parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
1291     parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
1292     parameter RXBUF_RESET_ON_EIDLE = "FALSE";
1293     parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
1294     parameter integer RXBUF_THRESH_OVFLW = 61;
1295     parameter RXBUF_THRESH_OVRD = "FALSE";
1296     parameter integer RXBUF_THRESH_UNDFLW = 4;
1297     parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
1298     parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
1299     parameter [71:0] RXCDR_CFG = 72'h0B000023FF20400020;
1300     parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
1301     parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
1302     parameter [5:0] RXCDR_LOCK_CFG = 6'b010101;
1303     parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
1304     parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
1305     parameter [15:0] RXDLY_CFG = 16'h001F;
1306     parameter [8:0] RXDLY_LCFG = 9'h030;
1307     parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
1308     parameter RXGEARBOX_EN = "FALSE";
1309     parameter [4:0] RXISCANRESET_TIME = 5'b00001;
1310     parameter [13:0] RXLPM_HF_CFG = 14'b00000011110000;
1311     parameter [13:0] RXLPM_LF_CFG = 14'b00000011110000;
1312     parameter [6:0] RXOOB_CFG = 7'b0000110;
1313     parameter integer RXOUT_DIV = 2;
1314     parameter [4:0] RXPCSRESET_TIME = 5'b00001;
1315     parameter [23:0] RXPHDLY_CFG = 24'h084020;
1316     parameter [23:0] RXPH_CFG = 24'h000000;
1317     parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
1318     parameter [4:0] RXPMARESET_TIME = 5'b00011;
1319     parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
1320     parameter integer RXSLIDE_AUTO_WAIT = 7;
1321     parameter RXSLIDE_MODE = "OFF";
1322     parameter [11:0] RX_BIAS_CFG = 12'b000000000000;
1323     parameter [5:0] RX_BUFFER_CFG = 6'b000000;
1324     parameter integer RX_CLK25_DIV = 7;
1325     parameter [0:0] RX_CLKMUX_PD = 1'b1;
1326     parameter [1:0] RX_CM_SEL = 2'b11;
1327     parameter [2:0] RX_CM_TRIM = 3'b100;
1328     parameter integer RX_DATA_WIDTH = 20;
1329     parameter [5:0] RX_DDI_SEL = 6'b000000;
1330     parameter [11:0] RX_DEBUG_CFG = 12'b000000000000;
1331     parameter RX_DEFER_RESET_BUF_EN = "TRUE";
1332     parameter [22:0] RX_DFE_GAIN_CFG = 23'h180E0F;
1333     parameter [11:0] RX_DFE_H2_CFG = 12'b000111100000;
1334     parameter [11:0] RX_DFE_H3_CFG = 12'b000111100000;
1335     parameter [10:0] RX_DFE_H4_CFG = 11'b00011110000;
1336     parameter [10:0] RX_DFE_H5_CFG = 11'b00011110000;
1337     parameter [12:0] RX_DFE_KL_CFG = 13'b0001111110000;
1338     parameter [31:0] RX_DFE_KL_CFG2 = 32'h3008E56A;
1339     parameter [15:0] RX_DFE_LPM_CFG = 16'h0904;
1340     parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
1341     parameter [16:0] RX_DFE_UT_CFG = 17'b00111111000000000;
1342     parameter [16:0] RX_DFE_VP_CFG = 17'b00011111100000000;
1343     parameter [12:0] RX_DFE_XYD_CFG = 13'b0000000010000;
1344     parameter RX_DISPERR_SEQ_MATCH = "TRUE";
1345     parameter integer RX_INT_DATAWIDTH = 0;
1346     parameter [12:0] RX_OS_CFG = 13'b0001111110000;
1347     parameter integer RX_SIG_VALID_DLY = 10;
1348     parameter RX_XCLK_SEL = "RXREC";
1349     parameter integer SAS_MAX_COM = 64;
1350     parameter integer SAS_MIN_COM = 36;
1351     parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
1352     parameter [2:0] SATA_BURST_VAL = 3'b100;
1353     parameter SATA_CPLL_CFG = "VCO_3000MHZ";
1354     parameter [2:0] SATA_EIDLE_VAL = 3'b100;
1355     parameter integer SATA_MAX_BURST = 8;
1356     parameter integer SATA_MAX_INIT = 21;
1357     parameter integer SATA_MAX_WAKE = 7;
1358     parameter integer SATA_MIN_BURST = 4;
1359     parameter integer SATA_MIN_INIT = 12;
1360     parameter integer SATA_MIN_WAKE = 4;
1361     parameter SHOW_REALIGN_COMMA = "TRUE";
1362     parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001;
1363     parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
1364     parameter SIM_RESET_SPEEDUP = "TRUE";
1365     parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
1366     parameter SIM_VERSION = "4.0";
1367     parameter [4:0] TERM_RCAL_CFG = 5'b10000;
1368     parameter [0:0] TERM_RCAL_OVRD = 1'b0;
1369     parameter [7:0] TRANS_TIME_RATE = 8'h0E;
1370     parameter [31:0] TST_RSV = 32'h00000000;
1371     parameter TXBUF_EN = "TRUE";
1372     parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
1373     parameter [15:0] TXDLY_CFG = 16'h001F;
1374     parameter [8:0] TXDLY_LCFG = 9'h030;
1375     parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
1376     parameter TXGEARBOX_EN = "FALSE";
1377     parameter integer TXOUT_DIV = 2;
1378     parameter [4:0] TXPCSRESET_TIME = 5'b00001;
1379     parameter [23:0] TXPHDLY_CFG = 24'h084020;
1380     parameter [15:0] TXPH_CFG = 16'h0780;
1381     parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
1382     parameter [4:0] TXPMARESET_TIME = 5'b00001;
1383     parameter integer TX_CLK25_DIV = 7;
1384     parameter [0:0] TX_CLKMUX_PD = 1'b1;
1385     parameter integer TX_DATA_WIDTH = 20;
1386     parameter [4:0] TX_DEEMPH0 = 5'b00000;
1387     parameter [4:0] TX_DEEMPH1 = 5'b00000;
1388     parameter TX_DRIVE_MODE = "DIRECT";
1389     parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
1390     parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
1391     parameter integer TX_INT_DATAWIDTH = 0;
1392     parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
1393     parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
1394     parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
1395     parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
1396     parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
1397     parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
1398     parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
1399     parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
1400     parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
1401     parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
1402     parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
1403     parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
1404     parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
1405     parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
1406     parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
1407     parameter [2:0] TX_RXDETECT_REF = 3'b100;
1408     parameter TX_XCLK_SEL = "TXUSR";
1409     parameter [0:0] UCODEER_CLR = 1'b0;
1410     output CPLLFBCLKLOST;
1411     output CPLLLOCK;
1412     output CPLLREFCLKLOST;
1413     output DRPRDY;
1414     output EYESCANDATAERROR;
1415     output GTREFCLKMONITOR;
1416     output GTXTXN;
1417     output GTXTXP;
1418     output PHYSTATUS;
1419     output RXBYTEISALIGNED;
1420     output RXBYTEREALIGN;
1421     output RXCDRLOCK;
1422     output RXCHANBONDSEQ;
1423     output RXCHANISALIGNED;
1424     output RXCHANREALIGN;
1425     output RXCOMINITDET;
1426     output RXCOMMADET;
1427     output RXCOMSASDET;
1428     output RXCOMWAKEDET;
1429     output RXDATAVALID;
1430     output RXDLYSRESETDONE;
1431     output RXELECIDLE;
1432     output RXHEADERVALID;
1433     output RXOUTCLK;
1434     output RXOUTCLKFABRIC;
1435     output RXOUTCLKPCS;
1436     output RXPHALIGNDONE;
1437     output RXPRBSERR;
1438     output RXQPISENN;
1439     output RXQPISENP;
1440     output RXRATEDONE;
1441     output RXRESETDONE;
1442     output RXSTARTOFSEQ;
1443     output RXVALID;
1444     output TXCOMFINISH;
1445     output TXDLYSRESETDONE;
1446     output TXGEARBOXREADY;
1447     output TXOUTCLK;
1448     output TXOUTCLKFABRIC;
1449     output TXOUTCLKPCS;
1450     output TXPHALIGNDONE;
1451     output TXPHINITDONE;
1452     output TXQPISENN;
1453     output TXQPISENP;
1454     output TXRATEDONE;
1455     output TXRESETDONE;
1456     output [15:0] DRPDO;
1457     output [15:0] PCSRSVDOUT;
1458     output [1:0] RXCLKCORCNT;
1459     output [1:0] TXBUFSTATUS;
1460     output [2:0] RXBUFSTATUS;
1461     output [2:0] RXHEADER;
1462     output [2:0] RXSTATUS;
1463     output [4:0] RXCHBONDO;
1464     output [4:0] RXPHMONITOR;
1465     output [4:0] RXPHSLIPMONITOR;
1466     output [63:0] RXDATA;
1467     output [6:0] RXMONITOROUT;
1468     output [7:0] DMONITOROUT;
1469     output [7:0] RXCHARISCOMMA;
1470     output [7:0] RXCHARISK;
1471     output [7:0] RXDISPERR;
1472     output [7:0] RXNOTINTABLE;
1473     output [9:0] TSTOUT;
1474     input CFGRESET;
1475     (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *)
1476     input CPLLLOCKDETCLK;
1477     input CPLLLOCKEN;
1478     input CPLLPD;
1479     input CPLLRESET;
1480     (* invertible_pin = "IS_DRPCLK_INVERTED" *)
1481     input DRPCLK;
1482     input DRPEN;
1483     input DRPWE;
1484     input EYESCANMODE;
1485     input EYESCANRESET;
1486     input EYESCANTRIGGER;
1487     (* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
1488     input GTGREFCLK;
1489     input GTNORTHREFCLK0;
1490     input GTNORTHREFCLK1;
1491     input GTREFCLK0;
1492     input GTREFCLK1;
1493     input GTRESETSEL;
1494     input GTRXRESET;
1495     input GTSOUTHREFCLK0;
1496     input GTSOUTHREFCLK1;
1497     input GTTXRESET;
1498     input GTXRXN;
1499     input GTXRXP;
1500     input QPLLCLK;
1501     input QPLLREFCLK;
1502     input RESETOVRD;
1503     input RX8B10BEN;
1504     input RXBUFRESET;
1505     input RXCDRFREQRESET;
1506     input RXCDRHOLD;
1507     input RXCDROVRDEN;
1508     input RXCDRRESET;
1509     input RXCDRRESETRSV;
1510     input RXCHBONDEN;
1511     input RXCHBONDMASTER;
1512     input RXCHBONDSLAVE;
1513     input RXCOMMADETEN;
1514     input RXDDIEN;
1515     input RXDFEAGCHOLD;
1516     input RXDFEAGCOVRDEN;
1517     input RXDFECM1EN;
1518     input RXDFELFHOLD;
1519     input RXDFELFOVRDEN;
1520     input RXDFELPMRESET;
1521     input RXDFETAP2HOLD;
1522     input RXDFETAP2OVRDEN;
1523     input RXDFETAP3HOLD;
1524     input RXDFETAP3OVRDEN;
1525     input RXDFETAP4HOLD;
1526     input RXDFETAP4OVRDEN;
1527     input RXDFETAP5HOLD;
1528     input RXDFETAP5OVRDEN;
1529     input RXDFEUTHOLD;
1530     input RXDFEUTOVRDEN;
1531     input RXDFEVPHOLD;
1532     input RXDFEVPOVRDEN;
1533     input RXDFEVSEN;
1534     input RXDFEXYDEN;
1535     input RXDFEXYDHOLD;
1536     input RXDFEXYDOVRDEN;
1537     input RXDLYBYPASS;
1538     input RXDLYEN;
1539     input RXDLYOVRDEN;
1540     input RXDLYSRESET;
1541     input RXGEARBOXSLIP;
1542     input RXLPMEN;
1543     input RXLPMHFHOLD;
1544     input RXLPMHFOVRDEN;
1545     input RXLPMLFHOLD;
1546     input RXLPMLFKLOVRDEN;
1547     input RXMCOMMAALIGNEN;
1548     input RXOOBRESET;
1549     input RXOSHOLD;
1550     input RXOSOVRDEN;
1551     input RXPCOMMAALIGNEN;
1552     input RXPCSRESET;
1553     input RXPHALIGN;
1554     input RXPHALIGNEN;
1555     input RXPHDLYPD;
1556     input RXPHDLYRESET;
1557     input RXPHOVRDEN;
1558     input RXPMARESET;
1559     input RXPOLARITY;
1560     input RXPRBSCNTRESET;
1561     input RXQPIEN;
1562     input RXSLIDE;
1563     input RXUSERRDY;
1564     (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
1565     input RXUSRCLK2;
1566     (* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
1567     input RXUSRCLK;
1568     input SETERRSTATUS;
1569     input TX8B10BEN;
1570     input TXCOMINIT;
1571     input TXCOMSAS;
1572     input TXCOMWAKE;
1573     input TXDEEMPH;
1574     input TXDETECTRX;
1575     input TXDIFFPD;
1576     input TXDLYBYPASS;
1577     input TXDLYEN;
1578     input TXDLYHOLD;
1579     input TXDLYOVRDEN;
1580     input TXDLYSRESET;
1581     input TXDLYUPDOWN;
1582     input TXELECIDLE;
1583     input TXINHIBIT;
1584     input TXPCSRESET;
1585     input TXPDELECIDLEMODE;
1586     input TXPHALIGN;
1587     input TXPHALIGNEN;
1588     input TXPHDLYPD;
1589     input TXPHDLYRESET;
1590     (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
1591     input TXPHDLYTSTCLK;
1592     input TXPHINIT;
1593     input TXPHOVRDEN;
1594     input TXPISOPD;
1595     input TXPMARESET;
1596     input TXPOLARITY;
1597     input TXPOSTCURSORINV;
1598     input TXPRBSFORCEERR;
1599     input TXPRECURSORINV;
1600     input TXQPIBIASEN;
1601     input TXQPISTRONGPDOWN;
1602     input TXQPIWEAKPUP;
1603     input TXSTARTSEQ;
1604     input TXSWING;
1605     input TXUSERRDY;
1606     (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
1607     input TXUSRCLK2;
1608     (* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
1609     input TXUSRCLK;
1610     input [15:0] DRPDI;
1611     input [15:0] GTRSVD;
1612     input [15:0] PCSRSVDIN;
1613     input [19:0] TSTIN;
1614     input [1:0] RXELECIDLEMODE;
1615     input [1:0] RXMONITORSEL;
1616     input [1:0] RXPD;
1617     input [1:0] RXSYSCLKSEL;
1618     input [1:0] TXPD;
1619     input [1:0] TXSYSCLKSEL;
1620     input [2:0] CPLLREFCLKSEL;
1621     input [2:0] LOOPBACK;
1622     input [2:0] RXCHBONDLEVEL;
1623     input [2:0] RXOUTCLKSEL;
1624     input [2:0] RXPRBSSEL;
1625     input [2:0] RXRATE;
1626     input [2:0] TXBUFDIFFCTRL;
1627     input [2:0] TXHEADER;
1628     input [2:0] TXMARGIN;
1629     input [2:0] TXOUTCLKSEL;
1630     input [2:0] TXPRBSSEL;
1631     input [2:0] TXRATE;
1632     input [3:0] CLKRSVD;
1633     input [3:0] TXDIFFCTRL;
1634     input [4:0] PCSRSVDIN2;
1635     input [4:0] PMARSVDIN2;
1636     input [4:0] PMARSVDIN;
1637     input [4:0] RXCHBONDI;
1638     input [4:0] TXPOSTCURSOR;
1639     input [4:0] TXPRECURSOR;
1640     input [63:0] TXDATA;
1641     input [6:0] TXMAINCURSOR;
1642     input [6:0] TXSEQUENCE;
1643     input [7:0] TX8B10BBYPASS;
1644     input [7:0] TXCHARDISPMODE;
1645     input [7:0] TXCHARDISPVAL;
1646     input [7:0] TXCHARISK;
1647     input [8:0] DRPADDR;
1648 endmodule
1649
1650 module GTXE2_COMMON (...);
1651     parameter [63:0] BIAS_CFG = 64'h0000040000001000;
1652     parameter [31:0] COMMON_CFG = 32'h00000000;
1653     parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
1654     parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
1655     parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0;
1656     parameter [26:0] QPLL_CFG = 27'h0680181;
1657     parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000;
1658     parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000;
1659     parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0;
1660     parameter [9:0] QPLL_CP = 10'b0000011111;
1661     parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0;
1662     parameter [0:0] QPLL_DMONITOR_SEL = 1'b0;
1663     parameter [9:0] QPLL_FBDIV = 10'b0000000000;
1664     parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0;
1665     parameter [0:0] QPLL_FBDIV_RATIO = 1'b0;
1666     parameter [23:0] QPLL_INIT_CFG = 24'h000006;
1667     parameter [15:0] QPLL_LOCK_CFG = 16'h21E8;
1668     parameter [3:0] QPLL_LPF = 4'b1111;
1669     parameter integer QPLL_REFCLK_DIV = 2;
1670     parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001;
1671     parameter SIM_RESET_SPEEDUP = "TRUE";
1672     parameter SIM_VERSION = "4.0";
1673     output DRPRDY;
1674     output QPLLFBCLKLOST;
1675     output QPLLLOCK;
1676     output QPLLOUTCLK;
1677     output QPLLOUTREFCLK;
1678     output QPLLREFCLKLOST;
1679     output REFCLKOUTMONITOR;
1680     output [15:0] DRPDO;
1681     output [7:0] QPLLDMONITOR;
1682     input BGBYPASSB;
1683     input BGMONITORENB;
1684     input BGPDB;
1685     (* invertible_pin = "IS_DRPCLK_INVERTED" *)
1686     input DRPCLK;
1687     input DRPEN;
1688     input DRPWE;
1689     (* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
1690     input GTGREFCLK;
1691     input GTNORTHREFCLK0;
1692     input GTNORTHREFCLK1;
1693     input GTREFCLK0;
1694     input GTREFCLK1;
1695     input GTSOUTHREFCLK0;
1696     input GTSOUTHREFCLK1;
1697     (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *)
1698     input QPLLLOCKDETCLK;
1699     input QPLLLOCKEN;
1700     input QPLLOUTRESET;
1701     input QPLLPD;
1702     input QPLLRESET;
1703     input RCALENB;
1704     input [15:0] DRPDI;
1705     input [15:0] QPLLRSVD1;
1706     input [2:0] QPLLREFCLKSEL;
1707     input [4:0] BGRCALOVRD;
1708     input [4:0] QPLLRSVD2;
1709     input [7:0] DRPADDR;
1710     input [7:0] PMARSVD;
1711 endmodule
1712
1713 module PCIE_2_1 (...);
1714     parameter [11:0] AER_BASE_PTR = 12'h140;
1715     parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
1716     parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
1717     parameter [15:0] AER_CAP_ID = 16'h0001;
1718     parameter AER_CAP_MULTIHEADER = "FALSE";
1719     parameter [11:0] AER_CAP_NEXTPTR = 12'h178;
1720     parameter AER_CAP_ON = "FALSE";
1721     parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000;
1722     parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE";
1723     parameter [3:0] AER_CAP_VERSION = 4'h2;
1724     parameter ALLOW_X8_GEN2 = "FALSE";
1725     parameter [31:0] BAR0 = 32'hFFFFFF00;
1726     parameter [31:0] BAR1 = 32'hFFFF0000;
1727     parameter [31:0] BAR2 = 32'hFFFF000C;
1728     parameter [31:0] BAR3 = 32'hFFFFFFFF;
1729     parameter [31:0] BAR4 = 32'h00000000;
1730     parameter [31:0] BAR5 = 32'h00000000;
1731     parameter [7:0] CAPABILITIES_PTR = 8'h40;
1732     parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000;
1733     parameter integer CFG_ECRC_ERR_CPLSTAT = 0;
1734     parameter [23:0] CLASS_CODE = 24'h000000;
1735     parameter CMD_INTX_IMPLEMENTED = "TRUE";
1736     parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE";
1737     parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0;
1738     parameter [6:0] CRM_MODULE_RSTS = 7'h00;
1739     parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE";
1740     parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE";
1741     parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE";
1742     parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE";
1743     parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE";
1744     parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE";
1745     parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE";
1746     parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE";
1747     parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0;
1748     parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE";
1749     parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0;
1750     parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE";
1751     parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE";
1752     parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
1753     parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0;
1754     parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
1755     parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE";
1756     parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2;
1757     parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0;
1758     parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE";
1759     parameter integer DEV_CAP_RSVD_14_12 = 0;
1760     parameter integer DEV_CAP_RSVD_17_16 = 0;
1761     parameter integer DEV_CAP_RSVD_31_29 = 0;
1762     parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE";
1763     parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE";
1764     parameter DISABLE_ASPM_L1_TIMER = "FALSE";
1765     parameter DISABLE_BAR_FILTERING = "FALSE";
1766     parameter DISABLE_ERR_MSG = "FALSE";
1767     parameter DISABLE_ID_CHECK = "FALSE";
1768     parameter DISABLE_LANE_REVERSAL = "FALSE";
1769     parameter DISABLE_LOCKED_FILTER = "FALSE";
1770     parameter DISABLE_PPM_FILTER = "FALSE";
1771     parameter DISABLE_RX_POISONED_RESP = "FALSE";
1772     parameter DISABLE_RX_TC_FILTER = "FALSE";
1773     parameter DISABLE_SCRAMBLING = "FALSE";
1774     parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
1775     parameter [11:0] DSN_BASE_PTR = 12'h100;
1776     parameter [15:0] DSN_CAP_ID = 16'h0003;
1777     parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C;
1778     parameter DSN_CAP_ON = "TRUE";
1779     parameter [3:0] DSN_CAP_VERSION = 4'h1;
1780     parameter [10:0] ENABLE_MSG_ROUTE = 11'h000;
1781     parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
1782     parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE";
1783     parameter ENTER_RVRY_EI_L0 = "TRUE";
1784     parameter EXIT_LOOPBACK_ON_EI = "TRUE";
1785     parameter [31:0] EXPANSION_ROM = 32'hFFFFF001;
1786     parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F;
1787     parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF;
1788     parameter [7:0] HEADER_TYPE = 8'h00;
1789     parameter [4:0] INFER_EI = 5'h00;
1790     parameter [7:0] INTERRUPT_PIN = 8'h01;
1791     parameter INTERRUPT_STAT_AUTO = "TRUE";
1792     parameter IS_SWITCH = "FALSE";
1793     parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF;
1794     parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE";
1795     parameter integer LINK_CAP_ASPM_SUPPORT = 1;
1796     parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE";
1797     parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE";
1798     parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
1799     parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
1800     parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
1801     parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
1802     parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
1803     parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
1804     parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
1805     parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
1806     parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE";
1807     parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1;
1808     parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08;
1809     parameter integer LINK_CAP_RSVD_23 = 0;
1810     parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE";
1811     parameter integer LINK_CONTROL_RCB = 0;
1812     parameter LINK_CTRL2_DEEMPHASIS = "FALSE";
1813     parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE";
1814     parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2;
1815     parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
1816     parameter [14:0] LL_ACK_TIMEOUT = 15'h0000;
1817     parameter LL_ACK_TIMEOUT_EN = "FALSE";
1818     parameter integer LL_ACK_TIMEOUT_FUNC = 0;
1819     parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000;
1820     parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
1821     parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
1822     parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01;
1823     parameter MPS_FORCE = "FALSE";
1824     parameter [7:0] MSIX_BASE_PTR = 8'h9C;
1825     parameter [7:0] MSIX_CAP_ID = 8'h11;
1826     parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00;
1827     parameter MSIX_CAP_ON = "FALSE";
1828     parameter integer MSIX_CAP_PBA_BIR = 0;
1829     parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050;
1830     parameter integer MSIX_CAP_TABLE_BIR = 0;
1831     parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040;
1832     parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000;
1833     parameter [7:0] MSI_BASE_PTR = 8'h48;
1834     parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE";
1835     parameter [7:0] MSI_CAP_ID = 8'h05;
1836     parameter integer MSI_CAP_MULTIMSGCAP = 0;
1837     parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0;
1838     parameter [7:0] MSI_CAP_NEXTPTR = 8'h60;
1839     parameter MSI_CAP_ON = "FALSE";
1840     parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE";
1841     parameter integer N_FTS_COMCLK_GEN1 = 255;
1842     parameter integer N_FTS_COMCLK_GEN2 = 255;
1843     parameter integer N_FTS_GEN1 = 255;
1844     parameter integer N_FTS_GEN2 = 255;
1845     parameter [7:0] PCIE_BASE_PTR = 8'h60;
1846     parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10;
1847     parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2;
1848     parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0;
1849     parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C;
1850     parameter PCIE_CAP_ON = "TRUE";
1851     parameter integer PCIE_CAP_RSVD_15_14 = 0;
1852     parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
1853     parameter integer PCIE_REVISION = 2;
1854     parameter integer PL_AUTO_CONFIG = 0;
1855     parameter PL_FAST_TRAIN = "FALSE";
1856     parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000;
1857     parameter PM_ASPML0S_TIMEOUT_EN = "FALSE";
1858     parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0;
1859     parameter PM_ASPM_FASTEXIT = "FALSE";
1860     parameter [7:0] PM_BASE_PTR = 8'h40;
1861     parameter integer PM_CAP_AUXCURRENT = 0;
1862     parameter PM_CAP_D1SUPPORT = "TRUE";
1863     parameter PM_CAP_D2SUPPORT = "TRUE";
1864     parameter PM_CAP_DSI = "FALSE";
1865     parameter [7:0] PM_CAP_ID = 8'h01;
1866     parameter [7:0] PM_CAP_NEXTPTR = 8'h48;
1867     parameter PM_CAP_ON = "TRUE";
1868     parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F;
1869     parameter PM_CAP_PME_CLOCK = "FALSE";
1870     parameter integer PM_CAP_RSVD_04 = 0;
1871     parameter integer PM_CAP_VERSION = 3;
1872     parameter PM_CSR_B2B3 = "FALSE";
1873     parameter PM_CSR_BPCCEN = "FALSE";
1874     parameter PM_CSR_NOSOFTRST = "TRUE";
1875     parameter [7:0] PM_DATA0 = 8'h01;
1876     parameter [7:0] PM_DATA1 = 8'h01;
1877     parameter [7:0] PM_DATA2 = 8'h01;
1878     parameter [7:0] PM_DATA3 = 8'h01;
1879     parameter [7:0] PM_DATA4 = 8'h01;
1880     parameter [7:0] PM_DATA5 = 8'h01;
1881     parameter [7:0] PM_DATA6 = 8'h01;
1882     parameter [7:0] PM_DATA7 = 8'h01;
1883     parameter [1:0] PM_DATA_SCALE0 = 2'h1;
1884     parameter [1:0] PM_DATA_SCALE1 = 2'h1;
1885     parameter [1:0] PM_DATA_SCALE2 = 2'h1;
1886     parameter [1:0] PM_DATA_SCALE3 = 2'h1;
1887     parameter [1:0] PM_DATA_SCALE4 = 2'h1;
1888     parameter [1:0] PM_DATA_SCALE5 = 2'h1;
1889     parameter [1:0] PM_DATA_SCALE6 = 2'h1;
1890     parameter [1:0] PM_DATA_SCALE7 = 2'h1;
1891     parameter PM_MF = "FALSE";
1892     parameter [11:0] RBAR_BASE_PTR = 12'h178;
1893     parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00;
1894     parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00;
1895     parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00;
1896     parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00;
1897     parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00;
1898     parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00;
1899     parameter [15:0] RBAR_CAP_ID = 16'h0015;
1900     parameter [2:0] RBAR_CAP_INDEX0 = 3'h0;
1901     parameter [2:0] RBAR_CAP_INDEX1 = 3'h0;
1902     parameter [2:0] RBAR_CAP_INDEX2 = 3'h0;
1903     parameter [2:0] RBAR_CAP_INDEX3 = 3'h0;
1904     parameter [2:0] RBAR_CAP_INDEX4 = 3'h0;
1905     parameter [2:0] RBAR_CAP_INDEX5 = 3'h0;
1906     parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000;
1907     parameter RBAR_CAP_ON = "FALSE";
1908     parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000;
1909     parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000;
1910     parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000;
1911     parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000;
1912     parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000;
1913     parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000;
1914     parameter [3:0] RBAR_CAP_VERSION = 4'h1;
1915     parameter [2:0] RBAR_NUM = 3'h1;
1916     parameter integer RECRC_CHK = 0;
1917     parameter RECRC_CHK_TRIM = "FALSE";
1918     parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE";
1919     parameter [1:0] RP_AUTO_SPD = 2'h1;
1920     parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F;
1921     parameter SELECT_DLL_IF = "FALSE";
1922     parameter SIM_VERSION = "1.0";
1923     parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
1924     parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
1925     parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE";
1926     parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE";
1927     parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE";
1928     parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE";
1929     parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE";
1930     parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000;
1931     parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE";
1932     parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
1933     parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0;
1934     parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00;
1935     parameter integer SPARE_BIT0 = 0;
1936     parameter integer SPARE_BIT1 = 0;
1937     parameter integer SPARE_BIT2 = 0;
1938     parameter integer SPARE_BIT3 = 0;
1939     parameter integer SPARE_BIT4 = 0;
1940     parameter integer SPARE_BIT5 = 0;
1941     parameter integer SPARE_BIT6 = 0;
1942     parameter integer SPARE_BIT7 = 0;
1943     parameter integer SPARE_BIT8 = 0;
1944     parameter [7:0] SPARE_BYTE0 = 8'h00;
1945     parameter [7:0] SPARE_BYTE1 = 8'h00;
1946     parameter [7:0] SPARE_BYTE2 = 8'h00;
1947     parameter [7:0] SPARE_BYTE3 = 8'h00;
1948     parameter [31:0] SPARE_WORD0 = 32'h00000000;
1949     parameter [31:0] SPARE_WORD1 = 32'h00000000;
1950     parameter [31:0] SPARE_WORD2 = 32'h00000000;
1951     parameter [31:0] SPARE_WORD3 = 32'h00000000;
1952     parameter SSL_MESSAGE_AUTO = "FALSE";
1953     parameter TECRC_EP_INV = "FALSE";
1954     parameter TL_RBYPASS = "FALSE";
1955     parameter integer TL_RX_RAM_RADDR_LATENCY = 0;
1956     parameter integer TL_RX_RAM_RDATA_LATENCY = 2;
1957     parameter integer TL_RX_RAM_WRITE_LATENCY = 0;
1958     parameter TL_TFC_DISABLE = "FALSE";
1959     parameter TL_TX_CHECKS_DISABLE = "FALSE";
1960     parameter integer TL_TX_RAM_RADDR_LATENCY = 0;
1961     parameter integer TL_TX_RAM_RDATA_LATENCY = 2;
1962     parameter integer TL_TX_RAM_WRITE_LATENCY = 0;
1963     parameter TRN_DW = "FALSE";
1964     parameter TRN_NP_FC = "FALSE";
1965     parameter UPCONFIG_CAPABLE = "TRUE";
1966     parameter UPSTREAM_FACING = "TRUE";
1967     parameter UR_ATOMIC = "TRUE";
1968     parameter UR_CFG1 = "TRUE";
1969     parameter UR_INV_REQ = "TRUE";
1970     parameter UR_PRS_RESPONSE = "TRUE";
1971     parameter USER_CLK2_DIV2 = "FALSE";
1972     parameter integer USER_CLK_FREQ = 3;
1973     parameter USE_RID_PINS = "FALSE";
1974     parameter VC0_CPL_INFINITE = "TRUE";
1975     parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF;
1976     parameter integer VC0_TOTAL_CREDITS_CD = 127;
1977     parameter integer VC0_TOTAL_CREDITS_CH = 31;
1978     parameter integer VC0_TOTAL_CREDITS_NPD = 24;
1979     parameter integer VC0_TOTAL_CREDITS_NPH = 12;
1980     parameter integer VC0_TOTAL_CREDITS_PD = 288;
1981     parameter integer VC0_TOTAL_CREDITS_PH = 32;
1982     parameter integer VC0_TX_LASTPACKET = 31;
1983     parameter [11:0] VC_BASE_PTR = 12'h10C;
1984     parameter [15:0] VC_CAP_ID = 16'h0002;
1985     parameter [11:0] VC_CAP_NEXTPTR = 12'h000;
1986     parameter VC_CAP_ON = "FALSE";
1987     parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE";
1988     parameter [3:0] VC_CAP_VERSION = 4'h1;
1989     parameter [11:0] VSEC_BASE_PTR = 12'h128;
1990     parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234;
1991     parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018;
1992     parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1;
1993     parameter [15:0] VSEC_CAP_ID = 16'h000B;
1994     parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE";
1995     parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140;
1996     parameter VSEC_CAP_ON = "FALSE";
1997     parameter [3:0] VSEC_CAP_VERSION = 4'h1;
1998     output CFGAERECRCCHECKEN;
1999     output CFGAERECRCGENEN;
2000     output CFGAERROOTERRCORRERRRECEIVED;
2001     output CFGAERROOTERRCORRERRREPORTINGEN;
2002     output CFGAERROOTERRFATALERRRECEIVED;
2003     output CFGAERROOTERRFATALERRREPORTINGEN;
2004     output CFGAERROOTERRNONFATALERRRECEIVED;
2005     output CFGAERROOTERRNONFATALERRREPORTINGEN;
2006     output CFGBRIDGESERREN;
2007     output CFGCOMMANDBUSMASTERENABLE;
2008     output CFGCOMMANDINTERRUPTDISABLE;
2009     output CFGCOMMANDIOENABLE;
2010     output CFGCOMMANDMEMENABLE;
2011     output CFGCOMMANDSERREN;
2012     output CFGDEVCONTROL2ARIFORWARDEN;
2013     output CFGDEVCONTROL2ATOMICEGRESSBLOCK;
2014     output CFGDEVCONTROL2ATOMICREQUESTEREN;
2015     output CFGDEVCONTROL2CPLTIMEOUTDIS;
2016     output CFGDEVCONTROL2IDOCPLEN;
2017     output CFGDEVCONTROL2IDOREQEN;
2018     output CFGDEVCONTROL2LTREN;
2019     output CFGDEVCONTROL2TLPPREFIXBLOCK;
2020     output CFGDEVCONTROLAUXPOWEREN;
2021     output CFGDEVCONTROLCORRERRREPORTINGEN;
2022     output CFGDEVCONTROLENABLERO;
2023     output CFGDEVCONTROLEXTTAGEN;
2024     output CFGDEVCONTROLFATALERRREPORTINGEN;
2025     output CFGDEVCONTROLNONFATALREPORTINGEN;
2026     output CFGDEVCONTROLNOSNOOPEN;
2027     output CFGDEVCONTROLPHANTOMEN;
2028     output CFGDEVCONTROLURERRREPORTINGEN;
2029     output CFGDEVSTATUSCORRERRDETECTED;
2030     output CFGDEVSTATUSFATALERRDETECTED;
2031     output CFGDEVSTATUSNONFATALERRDETECTED;
2032     output CFGDEVSTATUSURDETECTED;
2033     output CFGERRAERHEADERLOGSETN;
2034     output CFGERRCPLRDYN;
2035     output CFGINTERRUPTMSIENABLE;
2036     output CFGINTERRUPTMSIXENABLE;
2037     output CFGINTERRUPTMSIXFM;
2038     output CFGINTERRUPTRDYN;
2039     output CFGLINKCONTROLAUTOBANDWIDTHINTEN;
2040     output CFGLINKCONTROLBANDWIDTHINTEN;
2041     output CFGLINKCONTROLCLOCKPMEN;
2042     output CFGLINKCONTROLCOMMONCLOCK;
2043     output CFGLINKCONTROLEXTENDEDSYNC;
2044     output CFGLINKCONTROLHWAUTOWIDTHDIS;
2045     output CFGLINKCONTROLLINKDISABLE;
2046     output CFGLINKCONTROLRCB;
2047     output CFGLINKCONTROLRETRAINLINK;
2048     output CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
2049     output CFGLINKSTATUSBANDWIDTHSTATUS;
2050     output CFGLINKSTATUSDLLACTIVE;
2051     output CFGLINKSTATUSLINKTRAINING;
2052     output CFGMGMTRDWRDONEN;
2053     output CFGMSGRECEIVED;
2054     output CFGMSGRECEIVEDASSERTINTA;
2055     output CFGMSGRECEIVEDASSERTINTB;
2056     output CFGMSGRECEIVEDASSERTINTC;
2057     output CFGMSGRECEIVEDASSERTINTD;
2058     output CFGMSGRECEIVEDDEASSERTINTA;
2059     output CFGMSGRECEIVEDDEASSERTINTB;
2060     output CFGMSGRECEIVEDDEASSERTINTC;
2061     output CFGMSGRECEIVEDDEASSERTINTD;
2062     output CFGMSGRECEIVEDERRCOR;
2063     output CFGMSGRECEIVEDERRFATAL;
2064     output CFGMSGRECEIVEDERRNONFATAL;
2065     output CFGMSGRECEIVEDPMASNAK;
2066     output CFGMSGRECEIVEDPMETO;
2067     output CFGMSGRECEIVEDPMETOACK;
2068     output CFGMSGRECEIVEDPMPME;
2069     output CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
2070     output CFGMSGRECEIVEDUNLOCK;
2071     output CFGPMCSRPMEEN;
2072     output CFGPMCSRPMESTATUS;
2073     output CFGPMRCVASREQL1N;
2074     output CFGPMRCVENTERL1N;
2075     output CFGPMRCVENTERL23N;
2076     output CFGPMRCVREQACKN;
2077     output CFGROOTCONTROLPMEINTEN;
2078     output CFGROOTCONTROLSYSERRCORRERREN;
2079     output CFGROOTCONTROLSYSERRFATALERREN;
2080     output CFGROOTCONTROLSYSERRNONFATALERREN;
2081     output CFGSLOTCONTROLELECTROMECHILCTLPULSE;
2082     output CFGTRANSACTION;
2083     output CFGTRANSACTIONTYPE;
2084     output DBGSCLRA;
2085     output DBGSCLRB;
2086     output DBGSCLRC;
2087     output DBGSCLRD;
2088     output DBGSCLRE;
2089     output DBGSCLRF;
2090     output DBGSCLRG;
2091     output DBGSCLRH;
2092     output DBGSCLRI;
2093     output DBGSCLRJ;
2094     output DBGSCLRK;
2095     output DRPRDY;
2096     output LL2BADDLLPERR;
2097     output LL2BADTLPERR;
2098     output LL2PROTOCOLERR;
2099     output LL2RECEIVERERR;
2100     output LL2REPLAYROERR;
2101     output LL2REPLAYTOERR;
2102     output LL2SUSPENDOK;
2103     output LL2TFCINIT1SEQ;
2104     output LL2TFCINIT2SEQ;
2105     output LL2TXIDLE;
2106     output LNKCLKEN;
2107     output MIMRXREN;
2108     output MIMRXWEN;
2109     output MIMTXREN;
2110     output MIMTXWEN;
2111     output PIPERX0POLARITY;
2112     output PIPERX1POLARITY;
2113     output PIPERX2POLARITY;
2114     output PIPERX3POLARITY;
2115     output PIPERX4POLARITY;
2116     output PIPERX5POLARITY;
2117     output PIPERX6POLARITY;
2118     output PIPERX7POLARITY;
2119     output PIPETX0COMPLIANCE;
2120     output PIPETX0ELECIDLE;
2121     output PIPETX1COMPLIANCE;
2122     output PIPETX1ELECIDLE;
2123     output PIPETX2COMPLIANCE;
2124     output PIPETX2ELECIDLE;
2125     output PIPETX3COMPLIANCE;
2126     output PIPETX3ELECIDLE;
2127     output PIPETX4COMPLIANCE;
2128     output PIPETX4ELECIDLE;
2129     output PIPETX5COMPLIANCE;
2130     output PIPETX5ELECIDLE;
2131     output PIPETX6COMPLIANCE;
2132     output PIPETX6ELECIDLE;
2133     output PIPETX7COMPLIANCE;
2134     output PIPETX7ELECIDLE;
2135     output PIPETXDEEMPH;
2136     output PIPETXRATE;
2137     output PIPETXRCVRDET;
2138     output PIPETXRESET;
2139     output PL2L0REQ;
2140     output PL2LINKUP;
2141     output PL2RECEIVERERR;
2142     output PL2RECOVERY;
2143     output PL2RXELECIDLE;
2144     output PL2SUSPENDOK;
2145     output PLDIRECTEDCHANGEDONE;
2146     output PLLINKGEN2CAP;
2147     output PLLINKPARTNERGEN2SUPPORTED;
2148     output PLLINKUPCFGCAP;
2149     output PLPHYLNKUPN;
2150     output PLRECEIVEDHOTRST;
2151     output PLSELLNKRATE;
2152     output RECEIVEDFUNCLVLRSTN;
2153     output TL2ASPMSUSPENDCREDITCHECKOK;
2154     output TL2ASPMSUSPENDREQ;
2155     output TL2ERRFCPE;
2156     output TL2ERRMALFORMED;
2157     output TL2ERRRXOVERFLOW;
2158     output TL2PPMSUSPENDOK;
2159     output TRNLNKUP;
2160     output TRNRECRCERR;
2161     output TRNREOF;
2162     output TRNRERRFWD;
2163     output TRNRSOF;
2164     output TRNRSRCDSC;
2165     output TRNRSRCRDY;
2166     output TRNTCFGREQ;
2167     output TRNTDLLPDSTRDY;
2168     output TRNTERRDROP;
2169     output USERRSTN;
2170     output [11:0] DBGVECC;
2171     output [11:0] PLDBGVEC;
2172     output [11:0] TRNFCCPLD;
2173     output [11:0] TRNFCNPD;
2174     output [11:0] TRNFCPD;
2175     output [127:0] TRNRD;
2176     output [12:0] MIMRXRADDR;
2177     output [12:0] MIMRXWADDR;
2178     output [12:0] MIMTXRADDR;
2179     output [12:0] MIMTXWADDR;
2180     output [15:0] CFGMSGDATA;
2181     output [15:0] DRPDO;
2182     output [15:0] PIPETX0DATA;
2183     output [15:0] PIPETX1DATA;
2184     output [15:0] PIPETX2DATA;
2185     output [15:0] PIPETX3DATA;
2186     output [15:0] PIPETX4DATA;
2187     output [15:0] PIPETX5DATA;
2188     output [15:0] PIPETX6DATA;
2189     output [15:0] PIPETX7DATA;
2190     output [1:0] CFGLINKCONTROLASPMCONTROL;
2191     output [1:0] CFGLINKSTATUSCURRENTSPEED;
2192     output [1:0] CFGPMCSRPOWERSTATE;
2193     output [1:0] PIPETX0CHARISK;
2194     output [1:0] PIPETX0POWERDOWN;
2195     output [1:0] PIPETX1CHARISK;
2196     output [1:0] PIPETX1POWERDOWN;
2197     output [1:0] PIPETX2CHARISK;
2198     output [1:0] PIPETX2POWERDOWN;
2199     output [1:0] PIPETX3CHARISK;
2200     output [1:0] PIPETX3POWERDOWN;
2201     output [1:0] PIPETX4CHARISK;
2202     output [1:0] PIPETX4POWERDOWN;
2203     output [1:0] PIPETX5CHARISK;
2204     output [1:0] PIPETX5POWERDOWN;
2205     output [1:0] PIPETX6CHARISK;
2206     output [1:0] PIPETX6POWERDOWN;
2207     output [1:0] PIPETX7CHARISK;
2208     output [1:0] PIPETX7POWERDOWN;
2209     output [1:0] PL2RXPMSTATE;
2210     output [1:0] PLLANEREVERSALMODE;
2211     output [1:0] PLRXPMSTATE;
2212     output [1:0] PLSELLNKWIDTH;
2213     output [1:0] TRNRDLLPSRCRDY;
2214     output [1:0] TRNRREM;
2215     output [2:0] CFGDEVCONTROLMAXPAYLOAD;
2216     output [2:0] CFGDEVCONTROLMAXREADREQ;
2217     output [2:0] CFGINTERRUPTMMENABLE;
2218     output [2:0] CFGPCIELINKSTATE;
2219     output [2:0] PIPETXMARGIN;
2220     output [2:0] PLINITIALLINKWIDTH;
2221     output [2:0] PLTXPMSTATE;
2222     output [31:0] CFGMGMTDO;
2223     output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL;
2224     output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH;
2225     output [3:0] TRNTDSTRDY;
2226     output [4:0] LL2LINKSTATUS;
2227     output [5:0] PLLTSSMSTATE;
2228     output [5:0] TRNTBUFAV;
2229     output [63:0] DBGVECA;
2230     output [63:0] DBGVECB;
2231     output [63:0] TL2ERRHDR;
2232     output [63:0] TRNRDLLPDATA;
2233     output [67:0] MIMRXWDATA;
2234     output [68:0] MIMTXWDATA;
2235     output [6:0] CFGTRANSACTIONADDR;
2236     output [6:0] CFGVCTCVCMAP;
2237     output [7:0] CFGINTERRUPTDO;
2238     output [7:0] TRNFCCPLH;
2239     output [7:0] TRNFCNPH;
2240     output [7:0] TRNFCPH;
2241     output [7:0] TRNRBARHIT;
2242     input CFGERRACSN;
2243     input CFGERRATOMICEGRESSBLOCKEDN;
2244     input CFGERRCORN;
2245     input CFGERRCPLABORTN;
2246     input CFGERRCPLTIMEOUTN;
2247     input CFGERRCPLUNEXPECTN;
2248     input CFGERRECRCN;
2249     input CFGERRINTERNALCORN;
2250     input CFGERRINTERNALUNCORN;
2251     input CFGERRLOCKEDN;
2252     input CFGERRMALFORMEDN;
2253     input CFGERRMCBLOCKEDN;
2254     input CFGERRNORECOVERYN;
2255     input CFGERRPOISONEDN;
2256     input CFGERRPOSTEDN;
2257     input CFGERRURN;
2258     input CFGFORCECOMMONCLOCKOFF;
2259     input CFGFORCEEXTENDEDSYNCON;
2260     input CFGINTERRUPTASSERTN;
2261     input CFGINTERRUPTN;
2262     input CFGINTERRUPTSTATN;
2263     input CFGMGMTRDENN;
2264     input CFGMGMTWRENN;
2265     input CFGMGMTWRREADONLYN;
2266     input CFGMGMTWRRW1CASRWN;
2267     input CFGPMFORCESTATEENN;
2268     input CFGPMHALTASPML0SN;
2269     input CFGPMHALTASPML1N;
2270     input CFGPMSENDPMETON;
2271     input CFGPMTURNOFFOKN;
2272     input CFGPMWAKEN;
2273     input CFGTRNPENDINGN;
2274     input CMRSTN;
2275     input CMSTICKYRSTN;
2276     input DBGSUBMODE;
2277     input DLRSTN;
2278     input DRPCLK;
2279     input DRPEN;
2280     input DRPWE;
2281     input FUNCLVLRSTN;
2282     input LL2SENDASREQL1;
2283     input LL2SENDENTERL1;
2284     input LL2SENDENTERL23;
2285     input LL2SENDPMACK;
2286     input LL2SUSPENDNOW;
2287     input LL2TLPRCV;
2288     input PIPECLK;
2289     input PIPERX0CHANISALIGNED;
2290     input PIPERX0ELECIDLE;
2291     input PIPERX0PHYSTATUS;
2292     input PIPERX0VALID;
2293     input PIPERX1CHANISALIGNED;
2294     input PIPERX1ELECIDLE;
2295     input PIPERX1PHYSTATUS;
2296     input PIPERX1VALID;
2297     input PIPERX2CHANISALIGNED;
2298     input PIPERX2ELECIDLE;
2299     input PIPERX2PHYSTATUS;
2300     input PIPERX2VALID;
2301     input PIPERX3CHANISALIGNED;
2302     input PIPERX3ELECIDLE;
2303     input PIPERX3PHYSTATUS;
2304     input PIPERX3VALID;
2305     input PIPERX4CHANISALIGNED;
2306     input PIPERX4ELECIDLE;
2307     input PIPERX4PHYSTATUS;
2308     input PIPERX4VALID;
2309     input PIPERX5CHANISALIGNED;
2310     input PIPERX5ELECIDLE;
2311     input PIPERX5PHYSTATUS;
2312     input PIPERX5VALID;
2313     input PIPERX6CHANISALIGNED;
2314     input PIPERX6ELECIDLE;
2315     input PIPERX6PHYSTATUS;
2316     input PIPERX6VALID;
2317     input PIPERX7CHANISALIGNED;
2318     input PIPERX7ELECIDLE;
2319     input PIPERX7PHYSTATUS;
2320     input PIPERX7VALID;
2321     input PLDIRECTEDLINKAUTON;
2322     input PLDIRECTEDLINKSPEED;
2323     input PLDIRECTEDLTSSMNEWVLD;
2324     input PLDIRECTEDLTSSMSTALL;
2325     input PLDOWNSTREAMDEEMPHSOURCE;
2326     input PLRSTN;
2327     input PLTRANSMITHOTRST;
2328     input PLUPSTREAMPREFERDEEMPH;
2329     input SYSRSTN;
2330     input TL2ASPMSUSPENDCREDITCHECK;
2331     input TL2PPMSUSPENDREQ;
2332     input TLRSTN;
2333     input TRNRDSTRDY;
2334     input TRNRFCPRET;
2335     input TRNRNPOK;
2336     input TRNRNPREQ;
2337     input TRNTCFGGNT;
2338     input TRNTDLLPSRCRDY;
2339     input TRNTECRCGEN;
2340     input TRNTEOF;
2341     input TRNTERRFWD;
2342     input TRNTSOF;
2343     input TRNTSRCDSC;
2344     input TRNTSRCRDY;
2345     input TRNTSTR;
2346     input USERCLK2;
2347     input USERCLK;
2348     input [127:0] CFGERRAERHEADERLOG;
2349     input [127:0] TRNTD;
2350     input [15:0] CFGDEVID;
2351     input [15:0] CFGSUBSYSID;
2352     input [15:0] CFGSUBSYSVENDID;
2353     input [15:0] CFGVENDID;
2354     input [15:0] DRPDI;
2355     input [15:0] PIPERX0DATA;
2356     input [15:0] PIPERX1DATA;
2357     input [15:0] PIPERX2DATA;
2358     input [15:0] PIPERX3DATA;
2359     input [15:0] PIPERX4DATA;
2360     input [15:0] PIPERX5DATA;
2361     input [15:0] PIPERX6DATA;
2362     input [15:0] PIPERX7DATA;
2363     input [1:0] CFGPMFORCESTATE;
2364     input [1:0] DBGMODE;
2365     input [1:0] PIPERX0CHARISK;
2366     input [1:0] PIPERX1CHARISK;
2367     input [1:0] PIPERX2CHARISK;
2368     input [1:0] PIPERX3CHARISK;
2369     input [1:0] PIPERX4CHARISK;
2370     input [1:0] PIPERX5CHARISK;
2371     input [1:0] PIPERX6CHARISK;
2372     input [1:0] PIPERX7CHARISK;
2373     input [1:0] PLDIRECTEDLINKCHANGE;
2374     input [1:0] PLDIRECTEDLINKWIDTH;
2375     input [1:0] TRNTREM;
2376     input [2:0] CFGDSFUNCTIONNUMBER;
2377     input [2:0] CFGFORCEMPS;
2378     input [2:0] PIPERX0STATUS;
2379     input [2:0] PIPERX1STATUS;
2380     input [2:0] PIPERX2STATUS;
2381     input [2:0] PIPERX3STATUS;
2382     input [2:0] PIPERX4STATUS;
2383     input [2:0] PIPERX5STATUS;
2384     input [2:0] PIPERX6STATUS;
2385     input [2:0] PIPERX7STATUS;
2386     input [2:0] PLDBGMODE;
2387     input [2:0] TRNFCSEL;
2388     input [31:0] CFGMGMTDI;
2389     input [31:0] TRNTDLLPDATA;
2390     input [3:0] CFGMGMTBYTEENN;
2391     input [47:0] CFGERRTLPCPLHEADER;
2392     input [4:0] CFGAERINTERRUPTMSGNUM;
2393     input [4:0] CFGDSDEVICENUMBER;
2394     input [4:0] CFGPCIECAPINTERRUPTMSGNUM;
2395     input [4:0] PL2DIRECTEDLSTATE;
2396     input [5:0] PLDIRECTEDLTSSMNEW;
2397     input [63:0] CFGDSN;
2398     input [67:0] MIMRXRDATA;
2399     input [68:0] MIMTXRDATA;
2400     input [7:0] CFGDSBUSNUMBER;
2401     input [7:0] CFGINTERRUPTDI;
2402     input [7:0] CFGPORTNUMBER;
2403     input [7:0] CFGREVID;
2404     input [8:0] DRPADDR;
2405     input [9:0] CFGMGMTDWADDR;
2406 endmodule
2407
2408 module PCIE_3_0 (...);
2409     parameter ARI_CAP_ENABLE = "FALSE";
2410     parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE";
2411     parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE";
2412     parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE";
2413     parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
2414     parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
2415     parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
2416     parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE";
2417     parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
2418     parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE";
2419     parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE";
2420     parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
2421     parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
2422     parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
2423     parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
2424     parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1;
2425     parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE";
2426     parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
2427     parameter LL_ACK_TIMEOUT_EN = "FALSE";
2428     parameter integer LL_ACK_TIMEOUT_FUNC = 0;
2429     parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000;
2430     parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
2431     parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000;
2432     parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
2433     parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000;
2434     parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
2435     parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000;
2436     parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
2437     parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
2438     parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
2439     parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
2440     parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA;
2441     parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
2442     parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
2443     parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
2444     parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
2445     parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
2446     parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
2447     parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
2448     parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
2449     parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03;
2450     parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
2451     parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00;
2452     parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
2453     parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03;
2454     parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
2455     parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
2456     parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
2457     parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03;
2458     parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
2459     parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
2460     parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
2461     parameter [7:0] PF0_BIST_REGISTER = 8'h00;
2462     parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50;
2463     parameter [23:0] PF0_CLASS_CODE = 24'h000000;
2464     parameter [15:0] PF0_DEVICE_ID = 16'h0000;
2465     parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
2466     parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
2467     parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
2468     parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
2469     parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
2470     parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
2471     parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
2472     parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
2473     parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
2474     parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
2475     parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
2476     parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
2477     parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000;
2478     parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
2479     parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
2480     parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
2481     parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
2482     parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
2483     parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
2484     parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
2485     parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
2486     parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
2487     parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
2488     parameter [3:0] PF0_DPA_CAP_VER = 4'h1;
2489     parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
2490     parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
2491     parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
2492     parameter [7:0] PF0_INTERRUPT_LINE = 8'h00;
2493     parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
2494     parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
2495     parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
2496     parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
2497     parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
2498     parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
2499     parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
2500     parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
2501     parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
2502     parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
2503     parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
2504     parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
2505     parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
2506     parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
2507     parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
2508     parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
2509     parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
2510     parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
2511     parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
2512     parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
2513     parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
2514     parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
2515     parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
2516     parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
2517     parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
2518     parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
2519     parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
2520     parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000;
2521     parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
2522     parameter [3:0] PF0_PB_CAP_VER = 4'h1;
2523     parameter [7:0] PF0_PM_CAP_ID = 8'h01;
2524     parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
2525     parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
2526     parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
2527     parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
2528     parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
2529     parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
2530     parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
2531     parameter PF0_RBAR_CAP_ENABLE = "FALSE";
2532     parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0;
2533     parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0;
2534     parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0;
2535     parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000;
2536     parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000;
2537     parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000;
2538     parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000;
2539     parameter [3:0] PF0_RBAR_CAP_VER = 4'h1;
2540     parameter [2:0] PF0_RBAR_NUM = 3'h1;
2541     parameter [7:0] PF0_REVISION_ID = 8'h00;
2542     parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
2543     parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
2544     parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
2545     parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
2546     parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
2547     parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
2548     parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
2549     parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
2550     parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
2551     parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
2552     parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
2553     parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
2554     parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
2555     parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
2556     parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
2557     parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
2558     parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
2559     parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
2560     parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
2561     parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
2562     parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000;
2563     parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
2564     parameter PF0_TPHR_CAP_ENABLE = "FALSE";
2565     parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
2566     parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
2567     parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
2568     parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
2569     parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
2570     parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
2571     parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
2572     parameter [3:0] PF0_VC_CAP_VER = 4'h1;
2573     parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
2574     parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
2575     parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
2576     parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
2577     parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
2578     parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03;
2579     parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
2580     parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00;
2581     parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
2582     parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03;
2583     parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
2584     parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
2585     parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
2586     parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03;
2587     parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
2588     parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
2589     parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
2590     parameter [7:0] PF1_BIST_REGISTER = 8'h00;
2591     parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50;
2592     parameter [23:0] PF1_CLASS_CODE = 24'h000000;
2593     parameter [15:0] PF1_DEVICE_ID = 16'h0000;
2594     parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
2595     parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000;
2596     parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
2597     parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
2598     parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
2599     parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
2600     parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
2601     parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
2602     parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
2603     parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
2604     parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
2605     parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
2606     parameter [3:0] PF1_DPA_CAP_VER = 4'h1;
2607     parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
2608     parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
2609     parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
2610     parameter [7:0] PF1_INTERRUPT_LINE = 8'h00;
2611     parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
2612     parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
2613     parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
2614     parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
2615     parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
2616     parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
2617     parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
2618     parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
2619     parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
2620     parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000;
2621     parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
2622     parameter [3:0] PF1_PB_CAP_VER = 4'h1;
2623     parameter [7:0] PF1_PM_CAP_ID = 8'h01;
2624     parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
2625     parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3;
2626     parameter PF1_RBAR_CAP_ENABLE = "FALSE";
2627     parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0;
2628     parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0;
2629     parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0;
2630     parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000;
2631     parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000;
2632     parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000;
2633     parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000;
2634     parameter [3:0] PF1_RBAR_CAP_VER = 4'h1;
2635     parameter [2:0] PF1_RBAR_NUM = 3'h1;
2636     parameter [7:0] PF1_REVISION_ID = 8'h00;
2637     parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
2638     parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
2639     parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
2640     parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
2641     parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
2642     parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
2643     parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
2644     parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
2645     parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
2646     parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
2647     parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
2648     parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
2649     parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
2650     parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
2651     parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
2652     parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
2653     parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
2654     parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
2655     parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
2656     parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
2657     parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000;
2658     parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
2659     parameter PF1_TPHR_CAP_ENABLE = "FALSE";
2660     parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
2661     parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
2662     parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
2663     parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
2664     parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
2665     parameter [3:0] PF1_TPHR_CAP_VER = 4'h1;
2666     parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
2667     parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE";
2668     parameter PL_DISABLE_SCRAMBLING = "FALSE";
2669     parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
2670     parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE";
2671     parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE";
2672     parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
2673     parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
2674     parameter PL_EQ_BYPASS_PHASE23 = "FALSE";
2675     parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
2676     parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00;
2677     parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00;
2678     parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00;
2679     parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00;
2680     parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00;
2681     parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00;
2682     parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00;
2683     parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00;
2684     parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4;
2685     parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8;
2686     parameter integer PL_N_FTS_COMCLK_GEN1 = 255;
2687     parameter integer PL_N_FTS_COMCLK_GEN2 = 255;
2688     parameter integer PL_N_FTS_COMCLK_GEN3 = 255;
2689     parameter integer PL_N_FTS_GEN1 = 255;
2690     parameter integer PL_N_FTS_GEN2 = 255;
2691     parameter integer PL_N_FTS_GEN3 = 255;
2692     parameter PL_SIM_FAST_LINK_TRAINING = "FALSE";
2693     parameter PL_UPSTREAM_FACING = "TRUE";
2694     parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC;
2695     parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000;
2696     parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
2697     parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000;
2698     parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0;
2699     parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064;
2700     parameter SIM_VERSION = "1.0";
2701     parameter integer SPARE_BIT0 = 0;
2702     parameter integer SPARE_BIT1 = 0;
2703     parameter integer SPARE_BIT2 = 0;
2704     parameter integer SPARE_BIT3 = 0;
2705     parameter integer SPARE_BIT4 = 0;
2706     parameter integer SPARE_BIT5 = 0;
2707     parameter integer SPARE_BIT6 = 0;
2708     parameter integer SPARE_BIT7 = 0;
2709     parameter integer SPARE_BIT8 = 0;
2710     parameter [7:0] SPARE_BYTE0 = 8'h00;
2711     parameter [7:0] SPARE_BYTE1 = 8'h00;
2712     parameter [7:0] SPARE_BYTE2 = 8'h00;
2713     parameter [7:0] SPARE_BYTE3 = 8'h00;
2714     parameter [31:0] SPARE_WORD0 = 32'h00000000;
2715     parameter [31:0] SPARE_WORD1 = 32'h00000000;
2716     parameter [31:0] SPARE_WORD2 = 32'h00000000;
2717     parameter [31:0] SPARE_WORD3 = 32'h00000000;
2718     parameter SRIOV_CAP_ENABLE = "FALSE";
2719     parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
2720     parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000;
2721     parameter [11:0] TL_CREDITS_CD = 12'h3E0;
2722     parameter [7:0] TL_CREDITS_CH = 8'h20;
2723     parameter [11:0] TL_CREDITS_NPD = 12'h028;
2724     parameter [7:0] TL_CREDITS_NPH = 8'h20;
2725     parameter [11:0] TL_CREDITS_PD = 12'h198;
2726     parameter [7:0] TL_CREDITS_PH = 8'h20;
2727     parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE";
2728     parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
2729     parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
2730     parameter TL_LEGACY_MODE_ENABLE = "FALSE";
2731     parameter TL_PF_ENABLE_REG = "FALSE";
2732     parameter TL_TAG_MGMT_ENABLE = "TRUE";
2733     parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000;
2734     parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50;
2735     parameter integer VF0_MSIX_CAP_PBA_BIR = 0;
2736     parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
2737     parameter integer VF0_MSIX_CAP_TABLE_BIR = 0;
2738     parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
2739     parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000;
2740     parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0;
2741     parameter [7:0] VF0_PM_CAP_ID = 8'h01;
2742     parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00;
2743     parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3;
2744     parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
2745     parameter VF0_TPHR_CAP_ENABLE = "FALSE";
2746     parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
2747     parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000;
2748     parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
2749     parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
2750     parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
2751     parameter [3:0] VF0_TPHR_CAP_VER = 4'h1;
2752     parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000;
2753     parameter integer VF1_MSIX_CAP_PBA_BIR = 0;
2754     parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
2755     parameter integer VF1_MSIX_CAP_TABLE_BIR = 0;
2756     parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
2757     parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000;
2758     parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0;
2759     parameter [7:0] VF1_PM_CAP_ID = 8'h01;
2760     parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00;
2761     parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3;
2762     parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
2763     parameter VF1_TPHR_CAP_ENABLE = "FALSE";
2764     parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
2765     parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000;
2766     parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
2767     parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
2768     parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
2769     parameter [3:0] VF1_TPHR_CAP_VER = 4'h1;
2770     parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000;
2771     parameter integer VF2_MSIX_CAP_PBA_BIR = 0;
2772     parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
2773     parameter integer VF2_MSIX_CAP_TABLE_BIR = 0;
2774     parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
2775     parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000;
2776     parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0;
2777     parameter [7:0] VF2_PM_CAP_ID = 8'h01;
2778     parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00;
2779     parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3;
2780     parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
2781     parameter VF2_TPHR_CAP_ENABLE = "FALSE";
2782     parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE";
2783     parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000;
2784     parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
2785     parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0;
2786     parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
2787     parameter [3:0] VF2_TPHR_CAP_VER = 4'h1;
2788     parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000;
2789     parameter integer VF3_MSIX_CAP_PBA_BIR = 0;
2790     parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
2791     parameter integer VF3_MSIX_CAP_TABLE_BIR = 0;
2792     parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
2793     parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000;
2794     parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0;
2795     parameter [7:0] VF3_PM_CAP_ID = 8'h01;
2796     parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00;
2797     parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3;
2798     parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
2799     parameter VF3_TPHR_CAP_ENABLE = "FALSE";
2800     parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE";
2801     parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000;
2802     parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
2803     parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0;
2804     parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
2805     parameter [3:0] VF3_TPHR_CAP_VER = 4'h1;
2806     parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000;
2807     parameter integer VF4_MSIX_CAP_PBA_BIR = 0;
2808     parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050;
2809     parameter integer VF4_MSIX_CAP_TABLE_BIR = 0;
2810     parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
2811     parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000;
2812     parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0;
2813     parameter [7:0] VF4_PM_CAP_ID = 8'h01;
2814     parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00;
2815     parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3;
2816     parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
2817     parameter VF4_TPHR_CAP_ENABLE = "FALSE";
2818     parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE";
2819     parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000;
2820     parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0;
2821     parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0;
2822     parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
2823     parameter [3:0] VF4_TPHR_CAP_VER = 4'h1;
2824     parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000;
2825     parameter integer VF5_MSIX_CAP_PBA_BIR = 0;
2826     parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050;
2827     parameter integer VF5_MSIX_CAP_TABLE_BIR = 0;
2828     parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
2829     parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000;
2830     parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0;
2831     parameter [7:0] VF5_PM_CAP_ID = 8'h01;
2832     parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00;
2833     parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3;
2834     parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
2835     parameter VF5_TPHR_CAP_ENABLE = "FALSE";
2836     parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE";
2837     parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000;
2838     parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0;
2839     parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0;
2840     parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
2841     parameter [3:0] VF5_TPHR_CAP_VER = 4'h1;
2842     output CFGERRCOROUT;
2843     output CFGERRFATALOUT;
2844     output CFGERRNONFATALOUT;
2845     output CFGEXTREADRECEIVED;
2846     output CFGEXTWRITERECEIVED;
2847     output CFGHOTRESETOUT;
2848     output CFGINPUTUPDATEDONE;
2849     output CFGINTERRUPTAOUTPUT;
2850     output CFGINTERRUPTBOUTPUT;
2851     output CFGINTERRUPTCOUTPUT;
2852     output CFGINTERRUPTDOUTPUT;
2853     output CFGINTERRUPTMSIFAIL;
2854     output CFGINTERRUPTMSIMASKUPDATE;
2855     output CFGINTERRUPTMSISENT;
2856     output CFGINTERRUPTMSIXFAIL;
2857     output CFGINTERRUPTMSIXSENT;
2858     output CFGINTERRUPTSENT;
2859     output CFGLOCALERROR;
2860     output CFGLTRENABLE;
2861     output CFGMCUPDATEDONE;
2862     output CFGMGMTREADWRITEDONE;
2863     output CFGMSGRECEIVED;
2864     output CFGMSGTRANSMITDONE;
2865     output CFGPERFUNCTIONUPDATEDONE;
2866     output CFGPHYLINKDOWN;
2867     output CFGPLSTATUSCHANGE;
2868     output CFGPOWERSTATECHANGEINTERRUPT;
2869     output CFGTPHSTTREADENABLE;
2870     output CFGTPHSTTWRITEENABLE;
2871     output DRPRDY;
2872     output MAXISCQTLAST;
2873     output MAXISCQTVALID;
2874     output MAXISRCTLAST;
2875     output MAXISRCTVALID;
2876     output PCIERQSEQNUMVLD;
2877     output PCIERQTAGVLD;
2878     output PIPERX0POLARITY;
2879     output PIPERX1POLARITY;
2880     output PIPERX2POLARITY;
2881     output PIPERX3POLARITY;
2882     output PIPERX4POLARITY;
2883     output PIPERX5POLARITY;
2884     output PIPERX6POLARITY;
2885     output PIPERX7POLARITY;
2886     output PIPETX0COMPLIANCE;
2887     output PIPETX0DATAVALID;
2888     output PIPETX0ELECIDLE;
2889     output PIPETX0STARTBLOCK;
2890     output PIPETX1COMPLIANCE;
2891     output PIPETX1DATAVALID;
2892     output PIPETX1ELECIDLE;
2893     output PIPETX1STARTBLOCK;
2894     output PIPETX2COMPLIANCE;
2895     output PIPETX2DATAVALID;
2896     output PIPETX2ELECIDLE;
2897     output PIPETX2STARTBLOCK;
2898     output PIPETX3COMPLIANCE;
2899     output PIPETX3DATAVALID;
2900     output PIPETX3ELECIDLE;
2901     output PIPETX3STARTBLOCK;
2902     output PIPETX4COMPLIANCE;
2903     output PIPETX4DATAVALID;
2904     output PIPETX4ELECIDLE;
2905     output PIPETX4STARTBLOCK;
2906     output PIPETX5COMPLIANCE;
2907     output PIPETX5DATAVALID;
2908     output PIPETX5ELECIDLE;
2909     output PIPETX5STARTBLOCK;
2910     output PIPETX6COMPLIANCE;
2911     output PIPETX6DATAVALID;
2912     output PIPETX6ELECIDLE;
2913     output PIPETX6STARTBLOCK;
2914     output PIPETX7COMPLIANCE;
2915     output PIPETX7DATAVALID;
2916     output PIPETX7ELECIDLE;
2917     output PIPETX7STARTBLOCK;
2918     output PIPETXDEEMPH;
2919     output PIPETXRCVRDET;
2920     output PIPETXRESET;
2921     output PIPETXSWING;
2922     output PLEQINPROGRESS;
2923     output [11:0] CFGFCCPLD;
2924     output [11:0] CFGFCNPD;
2925     output [11:0] CFGFCPD;
2926     output [11:0] CFGVFSTATUS;
2927     output [143:0] MIREPLAYRAMWRITEDATA;
2928     output [143:0] MIREQUESTRAMWRITEDATA;
2929     output [15:0] CFGPERFUNCSTATUSDATA;
2930     output [15:0] DBGDATAOUT;
2931     output [15:0] DRPDO;
2932     output [17:0] CFGVFPOWERSTATE;
2933     output [17:0] CFGVFTPHSTMODE;
2934     output [1:0] CFGDPASUBSTATECHANGE;
2935     output [1:0] CFGFLRINPROCESS;
2936     output [1:0] CFGINTERRUPTMSIENABLE;
2937     output [1:0] CFGINTERRUPTMSIXENABLE;
2938     output [1:0] CFGINTERRUPTMSIXMASK;
2939     output [1:0] CFGLINKPOWERSTATE;
2940     output [1:0] CFGOBFFENABLE;
2941     output [1:0] CFGPHYLINKSTATUS;
2942     output [1:0] CFGRCBSTATUS;
2943     output [1:0] CFGTPHREQUESTERENABLE;
2944     output [1:0] MIREPLAYRAMREADENABLE;
2945     output [1:0] MIREPLAYRAMWRITEENABLE;
2946     output [1:0] PCIERQTAGAV;
2947     output [1:0] PCIETFCNPDAV;
2948     output [1:0] PCIETFCNPHAV;
2949     output [1:0] PIPERX0EQCONTROL;
2950     output [1:0] PIPERX1EQCONTROL;
2951     output [1:0] PIPERX2EQCONTROL;
2952     output [1:0] PIPERX3EQCONTROL;
2953     output [1:0] PIPERX4EQCONTROL;
2954     output [1:0] PIPERX5EQCONTROL;
2955     output [1:0] PIPERX6EQCONTROL;
2956     output [1:0] PIPERX7EQCONTROL;
2957     output [1:0] PIPETX0CHARISK;
2958     output [1:0] PIPETX0EQCONTROL;
2959     output [1:0] PIPETX0POWERDOWN;
2960     output [1:0] PIPETX0SYNCHEADER;
2961     output [1:0] PIPETX1CHARISK;
2962     output [1:0] PIPETX1EQCONTROL;
2963     output [1:0] PIPETX1POWERDOWN;
2964     output [1:0] PIPETX1SYNCHEADER;
2965     output [1:0] PIPETX2CHARISK;
2966     output [1:0] PIPETX2EQCONTROL;
2967     output [1:0] PIPETX2POWERDOWN;
2968     output [1:0] PIPETX2SYNCHEADER;
2969     output [1:0] PIPETX3CHARISK;
2970     output [1:0] PIPETX3EQCONTROL;
2971     output [1:0] PIPETX3POWERDOWN;
2972     output [1:0] PIPETX3SYNCHEADER;
2973     output [1:0] PIPETX4CHARISK;
2974     output [1:0] PIPETX4EQCONTROL;
2975     output [1:0] PIPETX4POWERDOWN;
2976     output [1:0] PIPETX4SYNCHEADER;
2977     output [1:0] PIPETX5CHARISK;
2978     output [1:0] PIPETX5EQCONTROL;
2979     output [1:0] PIPETX5POWERDOWN;
2980     output [1:0] PIPETX5SYNCHEADER;
2981     output [1:0] PIPETX6CHARISK;
2982     output [1:0] PIPETX6EQCONTROL;
2983     output [1:0] PIPETX6POWERDOWN;
2984     output [1:0] PIPETX6SYNCHEADER;
2985     output [1:0] PIPETX7CHARISK;
2986     output [1:0] PIPETX7EQCONTROL;
2987     output [1:0] PIPETX7POWERDOWN;
2988     output [1:0] PIPETX7SYNCHEADER;
2989     output [1:0] PIPETXRATE;
2990     output [1:0] PLEQPHASE;
2991     output [255:0] MAXISCQTDATA;
2992     output [255:0] MAXISRCTDATA;
2993     output [2:0] CFGCURRENTSPEED;
2994     output [2:0] CFGMAXPAYLOAD;
2995     output [2:0] CFGMAXREADREQ;
2996     output [2:0] CFGTPHFUNCTIONNUM;
2997     output [2:0] PIPERX0EQPRESET;
2998     output [2:0] PIPERX1EQPRESET;
2999     output [2:0] PIPERX2EQPRESET;
3000     output [2:0] PIPERX3EQPRESET;
3001     output [2:0] PIPERX4EQPRESET;
3002     output [2:0] PIPERX5EQPRESET;
3003     output [2:0] PIPERX6EQPRESET;
3004     output [2:0] PIPERX7EQPRESET;
3005     output [2:0] PIPETXMARGIN;
3006     output [31:0] CFGEXTWRITEDATA;
3007     output [31:0] CFGINTERRUPTMSIDATA;
3008     output [31:0] CFGMGMTREADDATA;
3009     output [31:0] CFGTPHSTTWRITEDATA;
3010     output [31:0] PIPETX0DATA;
3011     output [31:0] PIPETX1DATA;
3012     output [31:0] PIPETX2DATA;
3013     output [31:0] PIPETX3DATA;
3014     output [31:0] PIPETX4DATA;
3015     output [31:0] PIPETX5DATA;
3016     output [31:0] PIPETX6DATA;
3017     output [31:0] PIPETX7DATA;
3018     output [3:0] CFGEXTWRITEBYTEENABLE;
3019     output [3:0] CFGNEGOTIATEDWIDTH;
3020     output [3:0] CFGTPHSTTWRITEBYTEVALID;
3021     output [3:0] MICOMPLETIONRAMREADENABLEL;
3022     output [3:0] MICOMPLETIONRAMREADENABLEU;
3023     output [3:0] MICOMPLETIONRAMWRITEENABLEL;
3024     output [3:0] MICOMPLETIONRAMWRITEENABLEU;
3025     output [3:0] MIREQUESTRAMREADENABLE;
3026     output [3:0] MIREQUESTRAMWRITEENABLE;
3027     output [3:0] PCIERQSEQNUM;
3028     output [3:0] PIPERX0EQLPTXPRESET;
3029     output [3:0] PIPERX1EQLPTXPRESET;
3030     output [3:0] PIPERX2EQLPTXPRESET;
3031     output [3:0] PIPERX3EQLPTXPRESET;
3032     output [3:0] PIPERX4EQLPTXPRESET;
3033     output [3:0] PIPERX5EQLPTXPRESET;
3034     output [3:0] PIPERX6EQLPTXPRESET;
3035     output [3:0] PIPERX7EQLPTXPRESET;
3036     output [3:0] PIPETX0EQPRESET;
3037     output [3:0] PIPETX1EQPRESET;
3038     output [3:0] PIPETX2EQPRESET;
3039     output [3:0] PIPETX3EQPRESET;
3040     output [3:0] PIPETX4EQPRESET;
3041     output [3:0] PIPETX5EQPRESET;
3042     output [3:0] PIPETX6EQPRESET;
3043     output [3:0] PIPETX7EQPRESET;
3044     output [3:0] SAXISCCTREADY;
3045     output [3:0] SAXISRQTREADY;
3046     output [4:0] CFGMSGRECEIVEDTYPE;
3047     output [4:0] CFGTPHSTTADDRESS;
3048     output [5:0] CFGFUNCTIONPOWERSTATE;
3049     output [5:0] CFGINTERRUPTMSIMMENABLE;
3050     output [5:0] CFGINTERRUPTMSIVFENABLE;
3051     output [5:0] CFGINTERRUPTMSIXVFENABLE;
3052     output [5:0] CFGINTERRUPTMSIXVFMASK;
3053     output [5:0] CFGLTSSMSTATE;
3054     output [5:0] CFGTPHSTMODE;
3055     output [5:0] CFGVFFLRINPROCESS;
3056     output [5:0] CFGVFTPHREQUESTERENABLE;
3057     output [5:0] PCIECQNPREQCOUNT;
3058     output [5:0] PCIERQTAG;
3059     output [5:0] PIPERX0EQLPLFFS;
3060     output [5:0] PIPERX1EQLPLFFS;
3061     output [5:0] PIPERX2EQLPLFFS;
3062     output [5:0] PIPERX3EQLPLFFS;
3063     output [5:0] PIPERX4EQLPLFFS;
3064     output [5:0] PIPERX5EQLPLFFS;
3065     output [5:0] PIPERX6EQLPLFFS;
3066     output [5:0] PIPERX7EQLPLFFS;
3067     output [5:0] PIPETX0EQDEEMPH;
3068     output [5:0] PIPETX1EQDEEMPH;
3069     output [5:0] PIPETX2EQDEEMPH;
3070     output [5:0] PIPETX3EQDEEMPH;
3071     output [5:0] PIPETX4EQDEEMPH;
3072     output [5:0] PIPETX5EQDEEMPH;
3073     output [5:0] PIPETX6EQDEEMPH;
3074     output [5:0] PIPETX7EQDEEMPH;
3075     output [71:0] MICOMPLETIONRAMWRITEDATAL;
3076     output [71:0] MICOMPLETIONRAMWRITEDATAU;
3077     output [74:0] MAXISRCTUSER;
3078     output [7:0] CFGEXTFUNCTIONNUMBER;
3079     output [7:0] CFGFCCPLH;
3080     output [7:0] CFGFCNPH;
3081     output [7:0] CFGFCPH;
3082     output [7:0] CFGFUNCTIONSTATUS;
3083     output [7:0] CFGMSGRECEIVEDDATA;
3084     output [7:0] MAXISCQTKEEP;
3085     output [7:0] MAXISRCTKEEP;
3086     output [7:0] PLGEN3PCSRXSLIDE;
3087     output [84:0] MAXISCQTUSER;
3088     output [8:0] MIREPLAYRAMADDRESS;
3089     output [8:0] MIREQUESTRAMREADADDRESSA;
3090     output [8:0] MIREQUESTRAMREADADDRESSB;
3091     output [8:0] MIREQUESTRAMWRITEADDRESSA;
3092     output [8:0] MIREQUESTRAMWRITEADDRESSB;
3093     output [9:0] CFGEXTREGISTERNUMBER;
3094     output [9:0] MICOMPLETIONRAMREADADDRESSAL;
3095     output [9:0] MICOMPLETIONRAMREADADDRESSAU;
3096     output [9:0] MICOMPLETIONRAMREADADDRESSBL;
3097     output [9:0] MICOMPLETIONRAMREADADDRESSBU;
3098     output [9:0] MICOMPLETIONRAMWRITEADDRESSAL;
3099     output [9:0] MICOMPLETIONRAMWRITEADDRESSAU;
3100     output [9:0] MICOMPLETIONRAMWRITEADDRESSBL;
3101     output [9:0] MICOMPLETIONRAMWRITEADDRESSBU;
3102     input CFGCONFIGSPACEENABLE;
3103     input CFGERRCORIN;
3104     input CFGERRUNCORIN;
3105     input CFGEXTREADDATAVALID;
3106     input CFGHOTRESETIN;
3107     input CFGINPUTUPDATEREQUEST;
3108     input CFGINTERRUPTMSITPHPRESENT;
3109     input CFGINTERRUPTMSIXINT;
3110     input CFGLINKTRAININGENABLE;
3111     input CFGMCUPDATEREQUEST;
3112     input CFGMGMTREAD;
3113     input CFGMGMTTYPE1CFGREGACCESS;
3114     input CFGMGMTWRITE;
3115     input CFGMSGTRANSMIT;
3116     input CFGPERFUNCTIONOUTPUTREQUEST;
3117     input CFGPOWERSTATECHANGEACK;
3118     input CFGREQPMTRANSITIONL23READY;
3119     input CFGTPHSTTREADDATAVALID;
3120     input CORECLK;
3121     input CORECLKMICOMPLETIONRAML;
3122     input CORECLKMICOMPLETIONRAMU;
3123     input CORECLKMIREPLAYRAM;
3124     input CORECLKMIREQUESTRAM;
3125     input DRPCLK;
3126     input DRPEN;
3127     input DRPWE;
3128     input MGMTRESETN;
3129     input MGMTSTICKYRESETN;
3130     input PCIECQNPREQ;
3131     input PIPECLK;
3132     input PIPERESETN;
3133     input PIPERX0DATAVALID;
3134     input PIPERX0ELECIDLE;
3135     input PIPERX0EQDONE;
3136     input PIPERX0EQLPADAPTDONE;
3137     input PIPERX0EQLPLFFSSEL;
3138     input PIPERX0PHYSTATUS;
3139     input PIPERX0STARTBLOCK;
3140     input PIPERX0VALID;
3141     input PIPERX1DATAVALID;
3142     input PIPERX1ELECIDLE;
3143     input PIPERX1EQDONE;
3144     input PIPERX1EQLPADAPTDONE;
3145     input PIPERX1EQLPLFFSSEL;
3146     input PIPERX1PHYSTATUS;
3147     input PIPERX1STARTBLOCK;
3148     input PIPERX1VALID;
3149     input PIPERX2DATAVALID;
3150     input PIPERX2ELECIDLE;
3151     input PIPERX2EQDONE;
3152     input PIPERX2EQLPADAPTDONE;
3153     input PIPERX2EQLPLFFSSEL;
3154     input PIPERX2PHYSTATUS;
3155     input PIPERX2STARTBLOCK;
3156     input PIPERX2VALID;
3157     input PIPERX3DATAVALID;
3158     input PIPERX3ELECIDLE;
3159     input PIPERX3EQDONE;
3160     input PIPERX3EQLPADAPTDONE;
3161     input PIPERX3EQLPLFFSSEL;
3162     input PIPERX3PHYSTATUS;
3163     input PIPERX3STARTBLOCK;
3164     input PIPERX3VALID;
3165     input PIPERX4DATAVALID;
3166     input PIPERX4ELECIDLE;
3167     input PIPERX4EQDONE;
3168     input PIPERX4EQLPADAPTDONE;
3169     input PIPERX4EQLPLFFSSEL;
3170     input PIPERX4PHYSTATUS;
3171     input PIPERX4STARTBLOCK;
3172     input PIPERX4VALID;
3173     input PIPERX5DATAVALID;
3174     input PIPERX5ELECIDLE;
3175     input PIPERX5EQDONE;
3176     input PIPERX5EQLPADAPTDONE;
3177     input PIPERX5EQLPLFFSSEL;
3178     input PIPERX5PHYSTATUS;
3179     input PIPERX5STARTBLOCK;
3180     input PIPERX5VALID;
3181     input PIPERX6DATAVALID;
3182     input PIPERX6ELECIDLE;
3183     input PIPERX6EQDONE;
3184     input PIPERX6EQLPADAPTDONE;
3185     input PIPERX6EQLPLFFSSEL;
3186     input PIPERX6PHYSTATUS;
3187     input PIPERX6STARTBLOCK;
3188     input PIPERX6VALID;
3189     input PIPERX7DATAVALID;
3190     input PIPERX7ELECIDLE;
3191     input PIPERX7EQDONE;
3192     input PIPERX7EQLPADAPTDONE;
3193     input PIPERX7EQLPLFFSSEL;
3194     input PIPERX7PHYSTATUS;
3195     input PIPERX7STARTBLOCK;
3196     input PIPERX7VALID;
3197     input PIPETX0EQDONE;
3198     input PIPETX1EQDONE;
3199     input PIPETX2EQDONE;
3200     input PIPETX3EQDONE;
3201     input PIPETX4EQDONE;
3202     input PIPETX5EQDONE;
3203     input PIPETX6EQDONE;
3204     input PIPETX7EQDONE;
3205     input PLDISABLESCRAMBLER;
3206     input PLEQRESETEIEOSCOUNT;
3207     input PLGEN3PCSDISABLE;
3208     input RECCLK;
3209     input RESETN;
3210     input SAXISCCTLAST;
3211     input SAXISCCTVALID;
3212     input SAXISRQTLAST;
3213     input SAXISRQTVALID;
3214     input USERCLK;
3215     input [10:0] DRPADDR;
3216     input [143:0] MICOMPLETIONRAMREADDATA;
3217     input [143:0] MIREPLAYRAMREADDATA;
3218     input [143:0] MIREQUESTRAMREADDATA;
3219     input [15:0] CFGDEVID;
3220     input [15:0] CFGSUBSYSID;
3221     input [15:0] CFGSUBSYSVENDID;
3222     input [15:0] CFGVENDID;
3223     input [15:0] DRPDI;
3224     input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET;
3225     input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET;
3226     input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET;
3227     input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET;
3228     input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET;
3229     input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET;
3230     input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET;
3231     input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET;
3232     input [17:0] PIPETX0EQCOEFF;
3233     input [17:0] PIPETX1EQCOEFF;
3234     input [17:0] PIPETX2EQCOEFF;
3235     input [17:0] PIPETX3EQCOEFF;
3236     input [17:0] PIPETX4EQCOEFF;
3237     input [17:0] PIPETX5EQCOEFF;
3238     input [17:0] PIPETX6EQCOEFF;
3239     input [17:0] PIPETX7EQCOEFF;
3240     input [18:0] CFGMGMTADDR;
3241     input [1:0] CFGFLRDONE;
3242     input [1:0] CFGINTERRUPTMSITPHTYPE;
3243     input [1:0] CFGINTERRUPTPENDING;
3244     input [1:0] PIPERX0CHARISK;
3245     input [1:0] PIPERX0SYNCHEADER;
3246     input [1:0] PIPERX1CHARISK;
3247     input [1:0] PIPERX1SYNCHEADER;
3248     input [1:0] PIPERX2CHARISK;
3249     input [1:0] PIPERX2SYNCHEADER;
3250     input [1:0] PIPERX3CHARISK;
3251     input [1:0] PIPERX3SYNCHEADER;
3252     input [1:0] PIPERX4CHARISK;
3253     input [1:0] PIPERX4SYNCHEADER;
3254     input [1:0] PIPERX5CHARISK;
3255     input [1:0] PIPERX5SYNCHEADER;
3256     input [1:0] PIPERX6CHARISK;
3257     input [1:0] PIPERX6SYNCHEADER;
3258     input [1:0] PIPERX7CHARISK;
3259     input [1:0] PIPERX7SYNCHEADER;
3260     input [21:0] MAXISCQTREADY;
3261     input [21:0] MAXISRCTREADY;
3262     input [255:0] SAXISCCTDATA;
3263     input [255:0] SAXISRQTDATA;
3264     input [2:0] CFGDSFUNCTIONNUMBER;
3265     input [2:0] CFGFCSEL;
3266     input [2:0] CFGINTERRUPTMSIATTR;
3267     input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
3268     input [2:0] CFGMSGTRANSMITTYPE;
3269     input [2:0] CFGPERFUNCSTATUSCONTROL;
3270     input [2:0] CFGPERFUNCTIONNUMBER;
3271     input [2:0] PIPERX0STATUS;
3272     input [2:0] PIPERX1STATUS;
3273     input [2:0] PIPERX2STATUS;
3274     input [2:0] PIPERX3STATUS;
3275     input [2:0] PIPERX4STATUS;
3276     input [2:0] PIPERX5STATUS;
3277     input [2:0] PIPERX6STATUS;
3278     input [2:0] PIPERX7STATUS;
3279     input [31:0] CFGEXTREADDATA;
3280     input [31:0] CFGINTERRUPTMSIINT;
3281     input [31:0] CFGINTERRUPTMSIXDATA;
3282     input [31:0] CFGMGMTWRITEDATA;
3283     input [31:0] CFGMSGTRANSMITDATA;
3284     input [31:0] CFGTPHSTTREADDATA;
3285     input [31:0] PIPERX0DATA;
3286     input [31:0] PIPERX1DATA;
3287     input [31:0] PIPERX2DATA;
3288     input [31:0] PIPERX3DATA;
3289     input [31:0] PIPERX4DATA;
3290     input [31:0] PIPERX5DATA;
3291     input [31:0] PIPERX6DATA;
3292     input [31:0] PIPERX7DATA;
3293     input [32:0] SAXISCCTUSER;
3294     input [3:0] CFGINTERRUPTINT;
3295     input [3:0] CFGINTERRUPTMSISELECT;
3296     input [3:0] CFGMGMTBYTEENABLE;
3297     input [4:0] CFGDSDEVICENUMBER;
3298     input [59:0] SAXISRQTUSER;
3299     input [5:0] CFGVFFLRDONE;
3300     input [5:0] PIPEEQFS;
3301     input [5:0] PIPEEQLF;
3302     input [63:0] CFGDSN;
3303     input [63:0] CFGINTERRUPTMSIPENDINGSTATUS;
3304     input [63:0] CFGINTERRUPTMSIXADDRESS;
3305     input [7:0] CFGDSBUSNUMBER;
3306     input [7:0] CFGDSPORTNUMBER;
3307     input [7:0] CFGREVID;
3308     input [7:0] PLGEN3PCSRXSYNCDONE;
3309     input [7:0] SAXISCCTKEEP;
3310     input [7:0] SAXISRQTKEEP;
3311     input [8:0] CFGINTERRUPTMSITPHSTTAG;
3312 endmodule
3313
3314 module XADC (...);
3315     parameter [15:0] INIT_40 = 16'h0;
3316     parameter [15:0] INIT_41 = 16'h0;
3317     parameter [15:0] INIT_42 = 16'h0800;
3318     parameter [15:0] INIT_43 = 16'h0;
3319     parameter [15:0] INIT_44 = 16'h0;
3320     parameter [15:0] INIT_45 = 16'h0;
3321     parameter [15:0] INIT_46 = 16'h0;
3322     parameter [15:0] INIT_47 = 16'h0;
3323     parameter [15:0] INIT_48 = 16'h0;
3324     parameter [15:0] INIT_49 = 16'h0;
3325     parameter [15:0] INIT_4A = 16'h0;
3326     parameter [15:0] INIT_4B = 16'h0;
3327     parameter [15:0] INIT_4C = 16'h0;
3328     parameter [15:0] INIT_4D = 16'h0;
3329     parameter [15:0] INIT_4E = 16'h0;
3330     parameter [15:0] INIT_4F = 16'h0;
3331     parameter [15:0] INIT_50 = 16'h0;
3332     parameter [15:0] INIT_51 = 16'h0;
3333     parameter [15:0] INIT_52 = 16'h0;
3334     parameter [15:0] INIT_53 = 16'h0;
3335     parameter [15:0] INIT_54 = 16'h0;
3336     parameter [15:0] INIT_55 = 16'h0;
3337     parameter [15:0] INIT_56 = 16'h0;
3338     parameter [15:0] INIT_57 = 16'h0;
3339     parameter [15:0] INIT_58 = 16'h0;
3340     parameter [15:0] INIT_59 = 16'h0;
3341     parameter [15:0] INIT_5A = 16'h0;
3342     parameter [15:0] INIT_5B = 16'h0;
3343     parameter [15:0] INIT_5C = 16'h0;
3344     parameter [15:0] INIT_5D = 16'h0;
3345     parameter [15:0] INIT_5E = 16'h0;
3346     parameter [15:0] INIT_5F = 16'h0;
3347     parameter IS_CONVSTCLK_INVERTED = 1'b0;
3348     parameter IS_DCLK_INVERTED = 1'b0;
3349     parameter SIM_DEVICE = "7SERIES";
3350     parameter SIM_MONITOR_FILE = "design.txt";
3351     output BUSY;
3352     output DRDY;
3353     output EOC;
3354     output EOS;
3355     output JTAGBUSY;
3356     output JTAGLOCKED;
3357     output JTAGMODIFIED;
3358     output OT;
3359     output [15:0] DO;
3360     output [7:0] ALM;
3361     output [4:0] CHANNEL;
3362     output [4:0] MUXADDR;
3363     input CONVST;
3364     (* invertible_pin = "IS_CONVSTCLK_INVERTED" *)
3365     input CONVSTCLK;
3366     (* invertible_pin = "IS_DCLK_INVERTED" *)
3367     input DCLK;
3368     input DEN;
3369     input DWE;
3370     input RESET;
3371     input VN;
3372     input VP;
3373     input [15:0] DI;
3374     input [15:0] VAUXN;
3375     input [15:0] VAUXP;
3376     input [6:0] DADDR;
3377 endmodule
3378
3379 module DSP48E1 (...);
3380     parameter integer ACASCREG = 1;
3381     parameter integer ADREG = 1;
3382     parameter integer ALUMODEREG = 1;
3383     parameter integer AREG = 1;
3384     parameter AUTORESET_PATDET = "NO_RESET";
3385     parameter A_INPUT = "DIRECT";
3386     parameter integer BCASCREG = 1;
3387     parameter integer BREG = 1;
3388     parameter B_INPUT = "DIRECT";
3389     parameter integer CARRYINREG = 1;
3390     parameter integer CARRYINSELREG = 1;
3391     parameter integer CREG = 1;
3392     parameter integer DREG = 1;
3393     parameter integer INMODEREG = 1;
3394     parameter integer MREG = 1;
3395     parameter integer OPMODEREG = 1;
3396     parameter integer PREG = 1;
3397     parameter SEL_MASK = "MASK";
3398     parameter SEL_PATTERN = "PATTERN";
3399     parameter USE_DPORT = "FALSE";
3400     parameter USE_MULT = "MULTIPLY";
3401     parameter USE_PATTERN_DETECT = "NO_PATDET";
3402     parameter USE_SIMD = "ONE48";
3403     parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
3404     parameter [47:0] PATTERN = 48'h000000000000;
3405     parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
3406     parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
3407     parameter [0:0] IS_CLK_INVERTED = 1'b0;
3408     parameter [4:0] IS_INMODE_INVERTED = 5'b0;
3409     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
3410     output [29:0] ACOUT;
3411     output [17:0] BCOUT;
3412     output CARRYCASCOUT;
3413     output [3:0] CARRYOUT;
3414     output MULTSIGNOUT;
3415     output OVERFLOW;
3416     output [47:0] P;
3417     output PATTERNBDETECT;
3418     output PATTERNDETECT;
3419     output [47:0] PCOUT;
3420     output UNDERFLOW;
3421     input [29:0] A;
3422     input [29:0] ACIN;
3423     (* invertible_pin = "IS_ALUMODE_INVERTED" *)
3424     input [3:0] ALUMODE;
3425     input [17:0] B;
3426     input [17:0] BCIN;
3427     input [47:0] C;
3428     input CARRYCASCIN;
3429     (* invertible_pin = "IS_CARRYIN_INVERTED" *)
3430     input CARRYIN;
3431     input [2:0] CARRYINSEL;
3432     input CEA1;
3433     input CEA2;
3434     input CEAD;
3435     input CEALUMODE;
3436     input CEB1;
3437     input CEB2;
3438     input CEC;
3439     input CECARRYIN;
3440     input CECTRL;
3441     input CED;
3442     input CEINMODE;
3443     input CEM;
3444     input CEP;
3445     (* clkbuf_sink *)
3446     (* invertible_pin = "IS_CLK_INVERTED" *)
3447     input CLK;
3448     input [24:0] D;
3449     (* invertible_pin = "IS_INMODE_INVERTED" *)
3450     input [4:0] INMODE;
3451     input MULTSIGNIN;
3452     (* invertible_pin = "IS_OPMODE_INVERTED" *)
3453     input [6:0] OPMODE;
3454     input [47:0] PCIN;
3455     input RSTA;
3456     input RSTALLCARRYIN;
3457     input RSTALUMODE;
3458     input RSTB;
3459     input RSTC;
3460     input RSTCTRL;
3461     input RSTD;
3462     input RSTINMODE;
3463     input RSTM;
3464     input RSTP;
3465 endmodule
3466
3467 module BUFGCE (...);
3468     parameter CE_TYPE = "SYNC";
3469     parameter [0:0] IS_CE_INVERTED = 1'b0;
3470     parameter [0:0] IS_I_INVERTED = 1'b0;
3471     (* clkbuf_driver *)
3472     output O;
3473     (* invertible_pin = "IS_CE_INVERTED" *)
3474     input CE;
3475     (* invertible_pin = "IS_I_INVERTED" *)
3476     input I;
3477 endmodule
3478
3479 module BUFGCE_1 (...);
3480     (* clkbuf_driver *)
3481     output O;
3482     input CE;
3483     input I;
3484 endmodule
3485
3486 module BUFGMUX (...);
3487     parameter CLK_SEL_TYPE = "SYNC";
3488     (* clkbuf_driver *)
3489     output O;
3490     input I0;
3491     input I1;
3492     input S;
3493 endmodule
3494
3495 module BUFGMUX_1 (...);
3496     parameter CLK_SEL_TYPE = "SYNC";
3497     (* clkbuf_driver *)
3498     output O;
3499     input I0;
3500     input I1;
3501     input S;
3502 endmodule
3503
3504 module BUFGMUX_CTRL (...);
3505     (* clkbuf_driver *)
3506     output O;
3507     input I0;
3508     input I1;
3509     input S;
3510 endmodule
3511
3512 module BUFH (...);
3513     (* clkbuf_driver *)
3514     output O;
3515     input I;
3516 endmodule
3517
3518 module BUFIO (...);
3519     (* clkbuf_driver *)
3520     output O;
3521     input I;
3522 endmodule
3523
3524 module BUFMR (...);
3525     (* clkbuf_driver *)
3526     output O;
3527     input I;
3528 endmodule
3529
3530 module BUFMRCE (...);
3531     parameter CE_TYPE = "SYNC";
3532     parameter integer INIT_OUT = 0;
3533     parameter [0:0] IS_CE_INVERTED = 1'b0;
3534     (* clkbuf_driver *)
3535     output O;
3536     (* invertible_pin = "IS_CE_INVERTED" *)
3537     input CE;
3538     input I;
3539 endmodule
3540
3541 module BUFR (...);
3542     parameter BUFR_DIVIDE = "BYPASS";
3543     parameter SIM_DEVICE = "7SERIES";
3544     (* clkbuf_driver *)
3545     output O;
3546     input CE;
3547     input CLR;
3548     input I;
3549 endmodule
3550
3551 module MMCME2_ADV (...);
3552     parameter BANDWIDTH = "OPTIMIZED";
3553     parameter real CLKFBOUT_MULT_F = 5.000;
3554     parameter real CLKFBOUT_PHASE = 0.000;
3555     parameter CLKFBOUT_USE_FINE_PS = "FALSE";
3556     parameter real CLKIN1_PERIOD = 0.000;
3557     parameter real CLKIN2_PERIOD = 0.000;
3558     parameter real CLKIN_FREQ_MAX = 1066.000;
3559     parameter real CLKIN_FREQ_MIN = 10.000;
3560     parameter real CLKOUT0_DIVIDE_F = 1.000;
3561     parameter real CLKOUT0_DUTY_CYCLE = 0.500;
3562     parameter real CLKOUT0_PHASE = 0.000;
3563     parameter CLKOUT0_USE_FINE_PS = "FALSE";
3564     parameter integer CLKOUT1_DIVIDE = 1;
3565     parameter real CLKOUT1_DUTY_CYCLE = 0.500;
3566     parameter real CLKOUT1_PHASE = 0.000;
3567     parameter CLKOUT1_USE_FINE_PS = "FALSE";
3568     parameter integer CLKOUT2_DIVIDE = 1;
3569     parameter real CLKOUT2_DUTY_CYCLE = 0.500;
3570     parameter real CLKOUT2_PHASE = 0.000;
3571     parameter CLKOUT2_USE_FINE_PS = "FALSE";
3572     parameter integer CLKOUT3_DIVIDE = 1;
3573     parameter real CLKOUT3_DUTY_CYCLE = 0.500;
3574     parameter real CLKOUT3_PHASE = 0.000;
3575     parameter CLKOUT3_USE_FINE_PS = "FALSE";
3576     parameter CLKOUT4_CASCADE = "FALSE";
3577     parameter integer CLKOUT4_DIVIDE = 1;
3578     parameter real CLKOUT4_DUTY_CYCLE = 0.500;
3579     parameter real CLKOUT4_PHASE = 0.000;
3580     parameter CLKOUT4_USE_FINE_PS = "FALSE";
3581     parameter integer CLKOUT5_DIVIDE = 1;
3582     parameter real CLKOUT5_DUTY_CYCLE = 0.500;
3583     parameter real CLKOUT5_PHASE = 0.000;
3584     parameter CLKOUT5_USE_FINE_PS = "FALSE";
3585     parameter integer CLKOUT6_DIVIDE = 1;
3586     parameter real CLKOUT6_DUTY_CYCLE = 0.500;
3587     parameter real CLKOUT6_PHASE = 0.000;
3588     parameter CLKOUT6_USE_FINE_PS = "FALSE";
3589     parameter real CLKPFD_FREQ_MAX = 550.000;
3590     parameter real CLKPFD_FREQ_MIN = 10.000;
3591     parameter COMPENSATION = "ZHOLD";
3592     parameter integer DIVCLK_DIVIDE = 1;
3593     parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
3594     parameter [0:0] IS_PSEN_INVERTED = 1'b0;
3595     parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0;
3596     parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
3597     parameter [0:0] IS_RST_INVERTED = 1'b0;
3598     parameter real REF_JITTER1 = 0.010;
3599     parameter real REF_JITTER2 = 0.010;
3600     parameter SS_EN = "FALSE";
3601     parameter SS_MODE = "CENTER_HIGH";
3602     parameter integer SS_MOD_PERIOD = 10000;
3603     parameter STARTUP_WAIT = "FALSE";
3604     parameter real VCOCLK_FREQ_MAX = 1600.000;
3605     parameter real VCOCLK_FREQ_MIN = 600.000;
3606     parameter STARTUP_WAIT = "FALSE";
3607     output CLKFBOUT;
3608     output CLKFBOUTB;
3609     output CLKFBSTOPPED;
3610     output CLKINSTOPPED;
3611     output CLKOUT0;
3612     output CLKOUT0B;
3613     output CLKOUT1;
3614     output CLKOUT1B;
3615     output CLKOUT2;
3616     output CLKOUT2B;
3617     output CLKOUT3;
3618     output CLKOUT3B;
3619     output CLKOUT4;
3620     output CLKOUT5;
3621     output CLKOUT6;
3622     output [15:0] DO;
3623     output DRDY;
3624     output LOCKED;
3625     output PSDONE;
3626     input CLKFBIN;
3627     input CLKIN1;
3628     input CLKIN2;
3629     (* invertible_pin = "IS_CLKINSEL_INVERTED" *)
3630     input CLKINSEL;
3631     input [6:0] DADDR;
3632     input DCLK;
3633     input DEN;
3634     input [15:0] DI;
3635     input DWE;
3636     input PSCLK;
3637     (* invertible_pin = "IS_PSEN_INVERTED" *)
3638     input PSEN;
3639     (* invertible_pin = "IS_PSINCDEC_INVERTED" *)
3640     input PSINCDEC;
3641     (* invertible_pin = "IS_PWRDWN_INVERTED" *)
3642     input PWRDWN;
3643     (* invertible_pin = "IS_RST_INVERTED" *)
3644     input RST;
3645 endmodule
3646
3647 module MMCME2_BASE (...);
3648     parameter BANDWIDTH = "OPTIMIZED";
3649     parameter real CLKFBOUT_MULT_F = 5.000;
3650     parameter real CLKFBOUT_PHASE = 0.000;
3651     parameter real CLKIN1_PERIOD = 0.000;
3652     parameter real CLKOUT0_DIVIDE_F = 1.000;
3653     parameter real CLKOUT0_DUTY_CYCLE = 0.500;
3654     parameter real CLKOUT0_PHASE = 0.000;
3655     parameter integer CLKOUT1_DIVIDE = 1;
3656     parameter real CLKOUT1_DUTY_CYCLE = 0.500;
3657     parameter real CLKOUT1_PHASE = 0.000;
3658     parameter integer CLKOUT2_DIVIDE = 1;
3659     parameter real CLKOUT2_DUTY_CYCLE = 0.500;
3660     parameter real CLKOUT2_PHASE = 0.000;
3661     parameter integer CLKOUT3_DIVIDE = 1;
3662     parameter real CLKOUT3_DUTY_CYCLE = 0.500;
3663     parameter real CLKOUT3_PHASE = 0.000;
3664     parameter CLKOUT4_CASCADE = "FALSE";
3665     parameter integer CLKOUT4_DIVIDE = 1;
3666     parameter real CLKOUT4_DUTY_CYCLE = 0.500;
3667     parameter real CLKOUT4_PHASE = 0.000;
3668     parameter integer CLKOUT5_DIVIDE = 1;
3669     parameter real CLKOUT5_DUTY_CYCLE = 0.500;
3670     parameter real CLKOUT5_PHASE = 0.000;
3671     parameter integer CLKOUT6_DIVIDE = 1;
3672     parameter real CLKOUT6_DUTY_CYCLE = 0.500;
3673     parameter real CLKOUT6_PHASE = 0.000;
3674     parameter integer DIVCLK_DIVIDE = 1;
3675     parameter real REF_JITTER1 = 0.010;
3676     parameter STARTUP_WAIT = "FALSE";
3677     output CLKFBOUT;
3678     output CLKFBOUTB;
3679     output CLKOUT0;
3680     output CLKOUT0B;
3681     output CLKOUT1;
3682     output CLKOUT1B;
3683     output CLKOUT2;
3684     output CLKOUT2B;
3685     output CLKOUT3;
3686     output CLKOUT3B;
3687     output CLKOUT4;
3688     output CLKOUT5;
3689     output CLKOUT6;
3690     output LOCKED;
3691     input CLKFBIN;
3692     input CLKIN1;
3693     input PWRDWN;
3694     input RST;
3695 endmodule
3696
3697 module PLLE2_ADV (...);
3698     parameter BANDWIDTH = "OPTIMIZED";
3699     parameter COMPENSATION = "ZHOLD";
3700     parameter STARTUP_WAIT = "FALSE";
3701     parameter integer CLKOUT0_DIVIDE = 1;
3702     parameter integer CLKOUT1_DIVIDE = 1;
3703     parameter integer CLKOUT2_DIVIDE = 1;
3704     parameter integer CLKOUT3_DIVIDE = 1;
3705     parameter integer CLKOUT4_DIVIDE = 1;
3706     parameter integer CLKOUT5_DIVIDE = 1;
3707     parameter integer DIVCLK_DIVIDE = 1;
3708     parameter integer CLKFBOUT_MULT = 5;
3709     parameter real CLKFBOUT_PHASE = 0.000;
3710     parameter real CLKIN1_PERIOD = 0.000;
3711     parameter real CLKIN2_PERIOD = 0.000;
3712     parameter real CLKOUT0_DUTY_CYCLE = 0.500;
3713     parameter real CLKOUT0_PHASE = 0.000;
3714     parameter real CLKOUT1_DUTY_CYCLE = 0.500;
3715     parameter real CLKOUT1_PHASE = 0.000;
3716     parameter real CLKOUT2_DUTY_CYCLE = 0.500;
3717     parameter real CLKOUT2_PHASE = 0.000;
3718     parameter real CLKOUT3_DUTY_CYCLE = 0.500;
3719     parameter real CLKOUT3_PHASE = 0.000;
3720     parameter real CLKOUT4_DUTY_CYCLE = 0.500;
3721     parameter real CLKOUT4_PHASE = 0.000;
3722     parameter real CLKOUT5_DUTY_CYCLE = 0.500;
3723     parameter real CLKOUT5_PHASE = 0.000;
3724     parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
3725     parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
3726     parameter [0:0] IS_RST_INVERTED = 1'b0;
3727     parameter real REF_JITTER1 = 0.010;
3728     parameter real REF_JITTER2 = 0.010;
3729     parameter real VCOCLK_FREQ_MAX = 2133.000;
3730     parameter real VCOCLK_FREQ_MIN = 800.000;
3731     parameter real CLKIN_FREQ_MAX = 1066.000;
3732     parameter real CLKIN_FREQ_MIN = 19.000;
3733     parameter real CLKPFD_FREQ_MAX = 550.0;
3734     parameter real CLKPFD_FREQ_MIN = 19.0;
3735     output CLKFBOUT;
3736     output CLKOUT0;
3737     output CLKOUT1;
3738     output CLKOUT2;
3739     output CLKOUT3;
3740     output CLKOUT4;
3741     output CLKOUT5;
3742     output DRDY;
3743     output LOCKED;
3744     output [15:0] DO;
3745     input CLKFBIN;
3746     input CLKIN1;
3747     input CLKIN2;
3748     (* invertible_pin = "IS_CLKINSEL_INVERTED" *)
3749     input CLKINSEL;
3750     input DCLK;
3751     input DEN;
3752     input DWE;
3753     (* invertible_pin = "IS_PWRDWN_INVERTED" *)
3754     input PWRDWN;
3755     (* invertible_pin = "IS_RST_INVERTED" *)
3756     input RST;
3757     input [15:0] DI;
3758     input [6:0] DADDR;
3759 endmodule
3760
3761 module PLLE2_BASE (...);
3762     parameter BANDWIDTH = "OPTIMIZED";
3763     parameter integer CLKFBOUT_MULT = 5;
3764     parameter real CLKFBOUT_PHASE = 0.000;
3765     parameter real CLKIN1_PERIOD = 0.000;
3766     parameter integer CLKOUT0_DIVIDE = 1;
3767     parameter real CLKOUT0_DUTY_CYCLE = 0.500;
3768     parameter real CLKOUT0_PHASE = 0.000;
3769     parameter integer CLKOUT1_DIVIDE = 1;
3770     parameter real CLKOUT1_DUTY_CYCLE = 0.500;
3771     parameter real CLKOUT1_PHASE = 0.000;
3772     parameter integer CLKOUT2_DIVIDE = 1;
3773     parameter real CLKOUT2_DUTY_CYCLE = 0.500;
3774     parameter real CLKOUT2_PHASE = 0.000;
3775     parameter integer CLKOUT3_DIVIDE = 1;
3776     parameter real CLKOUT3_DUTY_CYCLE = 0.500;
3777     parameter real CLKOUT3_PHASE = 0.000;
3778     parameter integer CLKOUT4_DIVIDE = 1;
3779     parameter real CLKOUT4_DUTY_CYCLE = 0.500;
3780     parameter real CLKOUT4_PHASE = 0.000;
3781     parameter integer CLKOUT5_DIVIDE = 1;
3782     parameter real CLKOUT5_DUTY_CYCLE = 0.500;
3783     parameter real CLKOUT5_PHASE = 0.000;
3784     parameter integer DIVCLK_DIVIDE = 1;
3785     parameter real REF_JITTER1 = 0.010;
3786     parameter STARTUP_WAIT = "FALSE";
3787     output CLKFBOUT;
3788     output CLKOUT0;
3789     output CLKOUT1;
3790     output CLKOUT2;
3791     output CLKOUT3;
3792     output CLKOUT4;
3793     output CLKOUT5;
3794     output LOCKED;
3795     input CLKFBIN;
3796     input CLKIN1;
3797     input PWRDWN;
3798     input RST;
3799 endmodule
3800
3801 (* keep *)
3802 module BSCANE2 (...);
3803     parameter DISABLE_JTAG = "FALSE";
3804     parameter integer JTAG_CHAIN = 1;
3805     output CAPTURE;
3806     output DRCK;
3807     output RESET;
3808     output RUNTEST;
3809     output SEL;
3810     output SHIFT;
3811     output TCK;
3812     output TDI;
3813     output TMS;
3814     output UPDATE;
3815     input TDO;
3816 endmodule
3817
3818 (* keep *)
3819 module CAPTUREE2 (...);
3820     parameter ONESHOT = "TRUE";
3821     input CAP;
3822     input CLK;
3823 endmodule
3824
3825 module DNA_PORT (...);
3826     parameter [56:0] SIM_DNA_VALUE = 57'h0;
3827     output DOUT;
3828     input CLK;
3829     input DIN;
3830     input READ;
3831     input SHIFT;
3832 endmodule
3833
3834 module EFUSE_USR (...);
3835     parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
3836     output [31:0] EFUSEUSR;
3837 endmodule
3838
3839 module FRAME_ECCE2 (...);
3840     parameter FARSRC = "EFAR";
3841     parameter FRAME_RBT_IN_FILENAME = "NONE";
3842     output CRCERROR;
3843     output ECCERROR;
3844     output ECCERRORSINGLE;
3845     output SYNDROMEVALID;
3846     output [12:0] SYNDROME;
3847     output [25:0] FAR;
3848     output [4:0] SYNBIT;
3849     output [6:0] SYNWORD;
3850 endmodule
3851
3852 (* keep *)
3853 module ICAPE2 (...);
3854     parameter [31:0] DEVICE_ID = 32'h04244093;
3855     parameter ICAP_WIDTH = "X32";
3856     parameter SIM_CFG_FILE_NAME = "NONE";
3857     output [31:0] O;
3858     input CLK;
3859     input CSIB;
3860     input RDWRB;
3861     input [31:0] I;
3862 endmodule
3863
3864 (* keep *)
3865 module STARTUPE2 (...);
3866     parameter PROG_USR = "FALSE";
3867     parameter real SIM_CCLK_FREQ = 0.0;
3868     output CFGCLK;
3869     output CFGMCLK;
3870     output EOS;
3871     output PREQ;
3872     input CLK;
3873     input GSR;
3874     input GTS;
3875     input KEYCLEARB;
3876     input PACK;
3877     input USRCCLKO;
3878     input USRCCLKTS;
3879     input USRDONEO;
3880     input USRDONETS;
3881 endmodule
3882
3883 module USR_ACCESSE2 (...);
3884     output CFGCLK;
3885     output DATAVALID;
3886     output [31:0] DATA;
3887 endmodule
3888
3889 (* keep *)
3890 module DCIRESET (...);
3891     output LOCKED;
3892     input RST;
3893 endmodule
3894
3895 module IBUF_IBUFDISABLE (...);
3896     parameter IBUF_LOW_PWR = "TRUE";
3897     parameter IOSTANDARD = "DEFAULT";
3898     parameter SIM_DEVICE = "7SERIES";
3899     parameter USE_IBUFDISABLE = "TRUE";
3900     output O;
3901     (* iopad_external_pin *)
3902     input I;
3903     input IBUFDISABLE;
3904 endmodule
3905
3906 module IBUF_INTERMDISABLE (...);
3907     parameter IBUF_LOW_PWR = "TRUE";
3908     parameter IOSTANDARD = "DEFAULT";
3909     parameter SIM_DEVICE = "7SERIES";
3910     parameter USE_IBUFDISABLE = "TRUE";
3911     output O;
3912     (* iopad_external_pin *)
3913     input I;
3914     input IBUFDISABLE;
3915     input INTERMDISABLE;
3916 endmodule
3917
3918 module IBUFDS (...);
3919     parameter CAPACITANCE = "DONT_CARE";
3920     parameter DIFF_TERM = "FALSE";
3921     parameter DQS_BIAS = "FALSE";
3922     parameter IBUF_DELAY_VALUE = "0";
3923     parameter IBUF_LOW_PWR = "TRUE";
3924     parameter IFD_DELAY_VALUE = "AUTO";
3925     parameter IOSTANDARD = "DEFAULT";
3926     output O;
3927     (* iopad_external_pin *)
3928     input I;
3929     (* iopad_external_pin *)
3930     input IB;
3931 endmodule
3932
3933 module IBUFDS_DIFF_OUT (...);
3934     parameter DIFF_TERM = "FALSE";
3935     parameter DQS_BIAS = "FALSE";
3936     parameter IBUF_LOW_PWR = "TRUE";
3937     parameter IOSTANDARD = "DEFAULT";
3938     output O;
3939     output OB;
3940     (* iopad_external_pin *)
3941     input I;
3942     (* iopad_external_pin *)
3943     input IB;
3944 endmodule
3945
3946 module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
3947     parameter DIFF_TERM = "FALSE";
3948     parameter DQS_BIAS = "FALSE";
3949     parameter IBUF_LOW_PWR = "TRUE";
3950     parameter IOSTANDARD = "DEFAULT";
3951     parameter SIM_DEVICE = "7SERIES";
3952     parameter USE_IBUFDISABLE = "TRUE";
3953     output O;
3954     output OB;
3955     (* iopad_external_pin *)
3956     input I;
3957     (* iopad_external_pin *)
3958     input IB;
3959     input IBUFDISABLE;
3960 endmodule
3961
3962 module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
3963     parameter DIFF_TERM = "FALSE";
3964     parameter DQS_BIAS = "FALSE";
3965     parameter IBUF_LOW_PWR = "TRUE";
3966     parameter IOSTANDARD = "DEFAULT";
3967     parameter SIM_DEVICE = "7SERIES";
3968     parameter USE_IBUFDISABLE = "TRUE";
3969     output O;
3970     output OB;
3971     (* iopad_external_pin *)
3972     input I;
3973     (* iopad_external_pin *)
3974     input IB;
3975     input IBUFDISABLE;
3976     input INTERMDISABLE;
3977 endmodule
3978
3979 module IBUFDS_GTE2 (...);
3980     parameter CLKCM_CFG = "TRUE";
3981     parameter CLKRCV_TRST = "TRUE";
3982     parameter CLKSWING_CFG = "TRUE";
3983     output O;
3984     output ODIV2;
3985     input CEB;
3986     (* iopad_external_pin *)
3987     input I;
3988     (* iopad_external_pin *)
3989     input IB;
3990 endmodule
3991
3992 module IBUFDS_IBUFDISABLE (...);
3993     parameter DIFF_TERM = "FALSE";
3994     parameter DQS_BIAS = "FALSE";
3995     parameter IBUF_LOW_PWR = "TRUE";
3996     parameter IOSTANDARD = "DEFAULT";
3997     parameter SIM_DEVICE = "7SERIES";
3998     parameter USE_IBUFDISABLE = "TRUE";
3999     output O;
4000     (* iopad_external_pin *)
4001     input I;
4002     (* iopad_external_pin *)
4003     input IB;
4004     input IBUFDISABLE;
4005 endmodule
4006
4007 module IBUFDS_INTERMDISABLE (...);
4008     parameter DIFF_TERM = "FALSE";
4009     parameter DQS_BIAS = "FALSE";
4010     parameter IBUF_LOW_PWR = "TRUE";
4011     parameter IOSTANDARD = "DEFAULT";
4012     parameter SIM_DEVICE = "7SERIES";
4013     parameter USE_IBUFDISABLE = "TRUE";
4014     output O;
4015     (* iopad_external_pin *)
4016     input I;
4017     (* iopad_external_pin *)
4018     input IB;
4019     input IBUFDISABLE;
4020     input INTERMDISABLE;
4021 endmodule
4022
4023 module IBUFG (...);
4024     parameter CAPACITANCE = "DONT_CARE";
4025     parameter IBUF_DELAY_VALUE = "0";
4026     parameter IBUF_LOW_PWR = "TRUE";
4027     parameter IOSTANDARD = "DEFAULT";
4028     output O;
4029     (* iopad_external_pin *)
4030     input I;
4031 endmodule
4032
4033 module IBUFGDS (...);
4034     parameter CAPACITANCE = "DONT_CARE";
4035     parameter DIFF_TERM = "FALSE";
4036     parameter IBUF_DELAY_VALUE = "0";
4037     parameter IBUF_LOW_PWR = "TRUE";
4038     parameter IOSTANDARD = "DEFAULT";
4039     output O;
4040     (* iopad_external_pin *)
4041     input I;
4042     (* iopad_external_pin *)
4043     input IB;
4044 endmodule
4045
4046 module IBUFGDS_DIFF_OUT (...);
4047     parameter DIFF_TERM = "FALSE";
4048     parameter DQS_BIAS = "FALSE";
4049     parameter IBUF_LOW_PWR = "TRUE";
4050     parameter IOSTANDARD = "DEFAULT";
4051     output O;
4052     output OB;
4053     (* iopad_external_pin *)
4054     input I;
4055     (* iopad_external_pin *)
4056     input IB;
4057 endmodule
4058
4059 (* keep *)
4060 module IDELAYCTRL (...);
4061     parameter SIM_DEVICE = "7SERIES";
4062     output RDY;
4063     (* clkbuf_sink *)
4064     input REFCLK;
4065     input RST;
4066 endmodule
4067
4068 module IDELAYE2 (...);
4069     parameter CINVCTRL_SEL = "FALSE";
4070     parameter DELAY_SRC = "IDATAIN";
4071     parameter HIGH_PERFORMANCE_MODE = "FALSE";
4072     parameter IDELAY_TYPE = "FIXED";
4073     parameter integer IDELAY_VALUE = 0;
4074     parameter [0:0] IS_C_INVERTED = 1'b0;
4075     parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
4076     parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
4077     parameter PIPE_SEL = "FALSE";
4078     parameter real REFCLK_FREQUENCY = 200.0;
4079     parameter SIGNAL_PATTERN = "DATA";
4080     parameter integer SIM_DELAY_D = 0;
4081     output [4:0] CNTVALUEOUT;
4082     output DATAOUT;
4083     (* clkbuf_sink *)
4084     (* invertible_pin = "IS_C_INVERTED" *)
4085     input C;
4086     input CE;
4087     input CINVCTRL;
4088     input [4:0] CNTVALUEIN;
4089     (* invertible_pin = "IS_DATAIN_INVERTED" *)
4090     input DATAIN;
4091     (* invertible_pin = "IS_IDATAIN_INVERTED" *)
4092     input IDATAIN;
4093     input INC;
4094     input LD;
4095     input LDPIPEEN;
4096     input REGRST;
4097 endmodule
4098
4099 module IN_FIFO (...);
4100     parameter integer ALMOST_EMPTY_VALUE = 1;
4101     parameter integer ALMOST_FULL_VALUE = 1;
4102     parameter ARRAY_MODE = "ARRAY_MODE_4_X_8";
4103     parameter SYNCHRONOUS_MODE = "FALSE";
4104     output ALMOSTEMPTY;
4105     output ALMOSTFULL;
4106     output EMPTY;
4107     output FULL;
4108     output [7:0] Q0;
4109     output [7:0] Q1;
4110     output [7:0] Q2;
4111     output [7:0] Q3;
4112     output [7:0] Q4;
4113     output [7:0] Q5;
4114     output [7:0] Q6;
4115     output [7:0] Q7;
4116     output [7:0] Q8;
4117     output [7:0] Q9;
4118     (* clkbuf_sink *)
4119     input RDCLK;
4120     input RDEN;
4121     input RESET;
4122     (* clkbuf_sink *)
4123     input WRCLK;
4124     input WREN;
4125     input [3:0] D0;
4126     input [3:0] D1;
4127     input [3:0] D2;
4128     input [3:0] D3;
4129     input [3:0] D4;
4130     input [3:0] D7;
4131     input [3:0] D8;
4132     input [3:0] D9;
4133     input [7:0] D5;
4134     input [7:0] D6;
4135 endmodule
4136
4137 module IOBUF (...);
4138     parameter integer DRIVE = 12;
4139     parameter IBUF_LOW_PWR = "TRUE";
4140     parameter IOSTANDARD = "DEFAULT";
4141     parameter SLEW = "SLOW";
4142     output O;
4143     (* iopad_external_pin *)
4144     inout IO;
4145     input I;
4146     input T;
4147 endmodule
4148
4149 module IOBUF_DCIEN (...);
4150     parameter integer DRIVE = 12;
4151     parameter IBUF_LOW_PWR = "TRUE";
4152     parameter IOSTANDARD = "DEFAULT";
4153     parameter SIM_DEVICE = "7SERIES";
4154     parameter SLEW = "SLOW";
4155     parameter USE_IBUFDISABLE = "TRUE";
4156     output O;
4157     (* iopad_external_pin *)
4158     inout IO;
4159     input DCITERMDISABLE;
4160     input I;
4161     input IBUFDISABLE;
4162     input T;
4163 endmodule
4164
4165 module IOBUF_INTERMDISABLE (...);
4166     parameter integer DRIVE = 12;
4167     parameter IBUF_LOW_PWR = "TRUE";
4168     parameter IOSTANDARD = "DEFAULT";
4169     parameter SIM_DEVICE = "7SERIES";
4170     parameter SLEW = "SLOW";
4171     parameter USE_IBUFDISABLE = "TRUE";
4172     output O;
4173     (* iopad_external_pin *)
4174     inout IO;
4175     input I;
4176     input IBUFDISABLE;
4177     input INTERMDISABLE;
4178     input T;
4179 endmodule
4180
4181 module IOBUFDS (...);
4182     parameter DIFF_TERM = "FALSE";
4183     parameter DQS_BIAS = "FALSE";
4184     parameter IBUF_LOW_PWR = "TRUE";
4185     parameter IOSTANDARD = "DEFAULT";
4186     parameter SLEW = "SLOW";
4187     output O;
4188     (* iopad_external_pin *)
4189     inout IO;
4190     inout IOB;
4191     input I;
4192     input T;
4193 endmodule
4194
4195 module IOBUFDS_DCIEN (...);
4196     parameter DIFF_TERM = "FALSE";
4197     parameter DQS_BIAS = "FALSE";
4198     parameter IBUF_LOW_PWR = "TRUE";
4199     parameter IOSTANDARD = "DEFAULT";
4200     parameter SIM_DEVICE = "7SERIES";
4201     parameter SLEW = "SLOW";
4202     parameter USE_IBUFDISABLE = "TRUE";
4203     output O;
4204     (* iopad_external_pin *)
4205     inout IO;
4206     (* iopad_external_pin *)
4207     inout IOB;
4208     input DCITERMDISABLE;
4209     input I;
4210     input IBUFDISABLE;
4211     input T;
4212 endmodule
4213
4214 module IOBUFDS_DIFF_OUT (...);
4215     parameter DIFF_TERM = "FALSE";
4216     parameter DQS_BIAS = "FALSE";
4217     parameter IBUF_LOW_PWR = "TRUE";
4218     parameter IOSTANDARD = "DEFAULT";
4219     output O;
4220     output OB;
4221     (* iopad_external_pin *)
4222     inout IO;
4223     (* iopad_external_pin *)
4224     inout IOB;
4225     input I;
4226     input TM;
4227     input TS;
4228 endmodule
4229
4230 module IOBUFDS_DIFF_OUT_DCIEN (...);
4231     parameter DIFF_TERM = "FALSE";
4232     parameter DQS_BIAS = "FALSE";
4233     parameter IBUF_LOW_PWR = "TRUE";
4234     parameter IOSTANDARD = "DEFAULT";
4235     parameter SIM_DEVICE = "7SERIES";
4236     parameter USE_IBUFDISABLE = "TRUE";
4237     output O;
4238     output OB;
4239     (* iopad_external_pin *)
4240     inout IO;
4241     (* iopad_external_pin *)
4242     inout IOB;
4243     input DCITERMDISABLE;
4244     input I;
4245     input IBUFDISABLE;
4246     input TM;
4247     input TS;
4248 endmodule
4249
4250 module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
4251     parameter DIFF_TERM = "FALSE";
4252     parameter DQS_BIAS = "FALSE";
4253     parameter IBUF_LOW_PWR = "TRUE";
4254     parameter IOSTANDARD = "DEFAULT";
4255     parameter SIM_DEVICE = "7SERIES";
4256     parameter USE_IBUFDISABLE = "TRUE";
4257     output O;
4258     output OB;
4259     (* iopad_external_pin *)
4260     inout IO;
4261     (* iopad_external_pin *)
4262     inout IOB;
4263     input I;
4264     input IBUFDISABLE;
4265     input INTERMDISABLE;
4266     input TM;
4267     input TS;
4268 endmodule
4269
4270 module IOBUFDS_INTERMDISABLE (...);
4271     parameter DIFF_TERM = "FALSE";
4272     parameter DQS_BIAS = "FALSE";
4273     parameter IBUF_LOW_PWR = "TRUE";
4274     parameter IOSTANDARD = "DEFAULT";
4275     parameter SIM_DEVICE = "7SERIES";
4276     parameter SLEW = "SLOW";
4277     parameter USE_IBUFDISABLE = "TRUE";
4278     output O;
4279     (* iopad_external_pin *)
4280     inout IO;
4281     (* iopad_external_pin *)
4282     inout IOB;
4283     input I;
4284     input IBUFDISABLE;
4285     input INTERMDISABLE;
4286     input T;
4287 endmodule
4288
4289 module ISERDESE2 (...);
4290     parameter DATA_RATE = "DDR";
4291     parameter integer DATA_WIDTH = 4;
4292     parameter DYN_CLKDIV_INV_EN = "FALSE";
4293     parameter DYN_CLK_INV_EN = "FALSE";
4294     parameter [0:0] INIT_Q1 = 1'b0;
4295     parameter [0:0] INIT_Q2 = 1'b0;
4296     parameter [0:0] INIT_Q3 = 1'b0;
4297     parameter [0:0] INIT_Q4 = 1'b0;
4298     parameter INTERFACE_TYPE = "MEMORY";
4299     parameter IOBDELAY = "NONE";
4300     parameter [0:0] IS_CLKB_INVERTED = 1'b0;
4301     parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0;
4302     parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
4303     parameter [0:0] IS_CLK_INVERTED = 1'b0;
4304     parameter [0:0] IS_D_INVERTED = 1'b0;
4305     parameter [0:0] IS_OCLKB_INVERTED = 1'b0;
4306     parameter [0:0] IS_OCLK_INVERTED = 1'b0;
4307     parameter integer NUM_CE = 2;
4308     parameter OFB_USED = "FALSE";
4309     parameter SERDES_MODE = "MASTER";
4310     parameter [0:0] SRVAL_Q1 = 1'b0;
4311     parameter [0:0] SRVAL_Q2 = 1'b0;
4312     parameter [0:0] SRVAL_Q3 = 1'b0;
4313     parameter [0:0] SRVAL_Q4 = 1'b0;
4314     output O;
4315     output Q1;
4316     output Q2;
4317     output Q3;
4318     output Q4;
4319     output Q5;
4320     output Q6;
4321     output Q7;
4322     output Q8;
4323     output SHIFTOUT1;
4324     output SHIFTOUT2;
4325     input BITSLIP;
4326     input CE1;
4327     input CE2;
4328     (* clkbuf_sink *)
4329     (* invertible_pin = "IS_CLK_INVERTED" *)
4330     input CLK;
4331     (* clkbuf_sink *)
4332     (* invertible_pin = "IS_CLKB_INVERTED" *)
4333     input CLKB;
4334     (* clkbuf_sink *)
4335     (* invertible_pin = "IS_CLKDIV_INVERTED" *)
4336     input CLKDIV;
4337     (* clkbuf_sink *)
4338     (* invertible_pin = "IS_CLKDIVP_INVERTED" *)
4339     input CLKDIVP;
4340     (* invertible_pin = "IS_D_INVERTED" *)
4341     input D;
4342     input DDLY;
4343     input DYNCLKDIVSEL;
4344     input DYNCLKSEL;
4345     (* clkbuf_sink *)
4346     (* invertible_pin = "IS_OCLK_INVERTED" *)
4347     input OCLK;
4348     (* clkbuf_sink *)
4349     (* invertible_pin = "IS_OCLKB_INVERTED" *)
4350     input OCLKB;
4351     input OFB;
4352     input RST;
4353     input SHIFTIN1;
4354     input SHIFTIN2;
4355 endmodule
4356
4357 module KEEPER (...);
4358     inout O;
4359 endmodule
4360
4361 module OBUFDS (...);
4362     parameter CAPACITANCE = "DONT_CARE";
4363     parameter IOSTANDARD = "DEFAULT";
4364     parameter SLEW = "SLOW";
4365     (* iopad_external_pin *)
4366     output O;
4367     (* iopad_external_pin *)
4368     output OB;
4369     input I;
4370 endmodule
4371
4372 module OBUFT (...);
4373     parameter CAPACITANCE = "DONT_CARE";
4374     parameter integer DRIVE = 12;
4375     parameter IOSTANDARD = "DEFAULT";
4376     parameter SLEW = "SLOW";
4377     (* iopad_external_pin *)
4378     output O;
4379     input I;
4380     input T;
4381 endmodule
4382
4383 module OBUFTDS (...);
4384     parameter CAPACITANCE = "DONT_CARE";
4385     parameter IOSTANDARD = "DEFAULT";
4386     parameter SLEW = "SLOW";
4387     (* iopad_external_pin *)
4388     output O;
4389     (* iopad_external_pin *)
4390     output OB;
4391     input I;
4392     input T;
4393 endmodule
4394
4395 module ODELAYE2 (...);
4396     parameter CINVCTRL_SEL = "FALSE";
4397     parameter DELAY_SRC = "ODATAIN";
4398     parameter HIGH_PERFORMANCE_MODE = "FALSE";
4399     parameter [0:0] IS_C_INVERTED = 1'b0;
4400     parameter [0:0] IS_ODATAIN_INVERTED = 1'b0;
4401     parameter ODELAY_TYPE = "FIXED";
4402     parameter integer ODELAY_VALUE = 0;
4403     parameter PIPE_SEL = "FALSE";
4404     parameter real REFCLK_FREQUENCY = 200.0;
4405     parameter SIGNAL_PATTERN = "DATA";
4406     parameter integer SIM_DELAY_D = 0;
4407     output [4:0] CNTVALUEOUT;
4408     output DATAOUT;
4409     (* clkbuf_sink *)
4410     (* invertible_pin = "IS_C_INVERTED" *)
4411     input C;
4412     input CE;
4413     input CINVCTRL;
4414     input CLKIN;
4415     input [4:0] CNTVALUEIN;
4416     input INC;
4417     input LD;
4418     input LDPIPEEN;
4419     (* invertible_pin = "IS_ODATAIN_INVERTED" *)
4420     input ODATAIN;
4421     input REGRST;
4422 endmodule
4423
4424 module OSERDESE2 (...);
4425     parameter DATA_RATE_OQ = "DDR";
4426     parameter DATA_RATE_TQ = "DDR";
4427     parameter integer DATA_WIDTH = 4;
4428     parameter [0:0] INIT_OQ = 1'b0;
4429     parameter [0:0] INIT_TQ = 1'b0;
4430     parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
4431     parameter [0:0] IS_CLK_INVERTED = 1'b0;
4432     parameter [0:0] IS_D1_INVERTED = 1'b0;
4433     parameter [0:0] IS_D2_INVERTED = 1'b0;
4434     parameter [0:0] IS_D3_INVERTED = 1'b0;
4435     parameter [0:0] IS_D4_INVERTED = 1'b0;
4436     parameter [0:0] IS_D5_INVERTED = 1'b0;
4437     parameter [0:0] IS_D6_INVERTED = 1'b0;
4438     parameter [0:0] IS_D7_INVERTED = 1'b0;
4439     parameter [0:0] IS_D8_INVERTED = 1'b0;
4440     parameter [0:0] IS_T1_INVERTED = 1'b0;
4441     parameter [0:0] IS_T2_INVERTED = 1'b0;
4442     parameter [0:0] IS_T3_INVERTED = 1'b0;
4443     parameter [0:0] IS_T4_INVERTED = 1'b0;
4444     parameter SERDES_MODE = "MASTER";
4445     parameter [0:0] SRVAL_OQ = 1'b0;
4446     parameter [0:0] SRVAL_TQ = 1'b0;
4447     parameter TBYTE_CTL = "FALSE";
4448     parameter TBYTE_SRC = "FALSE";
4449     parameter integer TRISTATE_WIDTH = 4;
4450     output OFB;
4451     output OQ;
4452     output SHIFTOUT1;
4453     output SHIFTOUT2;
4454     output TBYTEOUT;
4455     output TFB;
4456     output TQ;
4457     (* clkbuf_sink *)
4458     (* invertible_pin = "IS_CLK_INVERTED" *)
4459     input CLK;
4460     (* clkbuf_sink *)
4461     (* invertible_pin = "IS_CLKDIV_INVERTED" *)
4462     input CLKDIV;
4463     (* invertible_pin = "IS_D1_INVERTED" *)
4464     input D1;
4465     (* invertible_pin = "IS_D2_INVERTED" *)
4466     input D2;
4467     (* invertible_pin = "IS_D3_INVERTED" *)
4468     input D3;
4469     (* invertible_pin = "IS_D4_INVERTED" *)
4470     input D4;
4471     (* invertible_pin = "IS_D5_INVERTED" *)
4472     input D5;
4473     (* invertible_pin = "IS_D6_INVERTED" *)
4474     input D6;
4475     (* invertible_pin = "IS_D7_INVERTED" *)
4476     input D7;
4477     (* invertible_pin = "IS_D8_INVERTED" *)
4478     input D8;
4479     input OCE;
4480     input RST;
4481     input SHIFTIN1;
4482     input SHIFTIN2;
4483     (* invertible_pin = "IS_T1_INVERTED" *)
4484     input T1;
4485     (* invertible_pin = "IS_T2_INVERTED" *)
4486     input T2;
4487     (* invertible_pin = "IS_T3_INVERTED" *)
4488     input T3;
4489     (* invertible_pin = "IS_T4_INVERTED" *)
4490     input T4;
4491     input TBYTEIN;
4492     input TCE;
4493 endmodule
4494
4495 module OUT_FIFO (...);
4496     parameter integer ALMOST_EMPTY_VALUE = 1;
4497     parameter integer ALMOST_FULL_VALUE = 1;
4498     parameter ARRAY_MODE = "ARRAY_MODE_8_X_4";
4499     parameter OUTPUT_DISABLE = "FALSE";
4500     parameter SYNCHRONOUS_MODE = "FALSE";
4501     output ALMOSTEMPTY;
4502     output ALMOSTFULL;
4503     output EMPTY;
4504     output FULL;
4505     output [3:0] Q0;
4506     output [3:0] Q1;
4507     output [3:0] Q2;
4508     output [3:0] Q3;
4509     output [3:0] Q4;
4510     output [3:0] Q7;
4511     output [3:0] Q8;
4512     output [3:0] Q9;
4513     output [7:0] Q5;
4514     output [7:0] Q6;
4515     (* clkbuf_sink *)
4516     input RDCLK;
4517     input RDEN;
4518     input RESET;
4519     (* clkbuf_sink *)
4520     input WRCLK;
4521     input WREN;
4522     input [7:0] D0;
4523     input [7:0] D1;
4524     input [7:0] D2;
4525     input [7:0] D3;
4526     input [7:0] D4;
4527     input [7:0] D5;
4528     input [7:0] D6;
4529     input [7:0] D7;
4530     input [7:0] D8;
4531     input [7:0] D9;
4532 endmodule
4533
4534 module PHASER_IN (...);
4535     parameter integer CLKOUT_DIV = 4;
4536     parameter DQS_BIAS_MODE = "FALSE";
4537     parameter EN_ISERDES_RST = "FALSE";
4538     parameter integer FINE_DELAY = 0;
4539     parameter FREQ_REF_DIV = "NONE";
4540     parameter [0:0] IS_RST_INVERTED = 1'b0;
4541     parameter real MEMREFCLK_PERIOD = 0.000;
4542     parameter OUTPUT_CLK_SRC = "PHASE_REF";
4543     parameter real PHASEREFCLK_PERIOD = 0.000;
4544     parameter real REFCLK_PERIOD = 0.000;
4545     parameter integer SEL_CLK_OFFSET = 5;
4546     parameter SYNC_IN_DIV_RST = "FALSE";
4547     output FINEOVERFLOW;
4548     output ICLK;
4549     output ICLKDIV;
4550     output ISERDESRST;
4551     output RCLK;
4552     output [5:0] COUNTERREADVAL;
4553     input COUNTERLOADEN;
4554     input COUNTERREADEN;
4555     input DIVIDERST;
4556     input EDGEADV;
4557     input FINEENABLE;
4558     input FINEINC;
4559     input FREQREFCLK;
4560     input MEMREFCLK;
4561     input PHASEREFCLK;
4562     (* invertible_pin = "IS_RST_INVERTED" *)
4563     input RST;
4564     input SYNCIN;
4565     input SYSCLK;
4566     input [1:0] RANKSEL;
4567     input [5:0] COUNTERLOADVAL;
4568 endmodule
4569
4570 module PHASER_IN_PHY (...);
4571     parameter BURST_MODE = "FALSE";
4572     parameter integer CLKOUT_DIV = 4;
4573     parameter [0:0] DQS_AUTO_RECAL = 1'b1;
4574     parameter DQS_BIAS_MODE = "FALSE";
4575     parameter [2:0] DQS_FIND_PATTERN = 3'b001;
4576     parameter integer FINE_DELAY = 0;
4577     parameter FREQ_REF_DIV = "NONE";
4578     parameter [0:0] IS_RST_INVERTED = 1'b0;
4579     parameter real MEMREFCLK_PERIOD = 0.000;
4580     parameter OUTPUT_CLK_SRC = "PHASE_REF";
4581     parameter real PHASEREFCLK_PERIOD = 0.000;
4582     parameter real REFCLK_PERIOD = 0.000;
4583     parameter integer SEL_CLK_OFFSET = 5;
4584     parameter SYNC_IN_DIV_RST = "FALSE";
4585     parameter WR_CYCLES = "FALSE";
4586     output DQSFOUND;
4587     output DQSOUTOFRANGE;
4588     output FINEOVERFLOW;
4589     output ICLK;
4590     output ICLKDIV;
4591     output ISERDESRST;
4592     output PHASELOCKED;
4593     output RCLK;
4594     output WRENABLE;
4595     output [5:0] COUNTERREADVAL;
4596     input BURSTPENDINGPHY;
4597     input COUNTERLOADEN;
4598     input COUNTERREADEN;
4599     input FINEENABLE;
4600     input FINEINC;
4601     input FREQREFCLK;
4602     input MEMREFCLK;
4603     input PHASEREFCLK;
4604     (* invertible_pin = "IS_RST_INVERTED" *)
4605     input RST;
4606     input RSTDQSFIND;
4607     input SYNCIN;
4608     input SYSCLK;
4609     input [1:0] ENCALIBPHY;
4610     input [1:0] RANKSELPHY;
4611     input [5:0] COUNTERLOADVAL;
4612 endmodule
4613
4614 module PHASER_OUT (...);
4615     parameter integer CLKOUT_DIV = 4;
4616     parameter COARSE_BYPASS = "FALSE";
4617     parameter integer COARSE_DELAY = 0;
4618     parameter EN_OSERDES_RST = "FALSE";
4619     parameter integer FINE_DELAY = 0;
4620     parameter [0:0] IS_RST_INVERTED = 1'b0;
4621     parameter real MEMREFCLK_PERIOD = 0.000;
4622     parameter OCLKDELAY_INV = "FALSE";
4623     parameter integer OCLK_DELAY = 0;
4624     parameter OUTPUT_CLK_SRC = "PHASE_REF";
4625     parameter real PHASEREFCLK_PERIOD = 0.000;
4626     parameter [2:0] PO = 3'b000;
4627     parameter real REFCLK_PERIOD = 0.000;
4628     parameter SYNC_IN_DIV_RST = "FALSE";
4629     output COARSEOVERFLOW;
4630     output FINEOVERFLOW;
4631     output OCLK;
4632     output OCLKDELAYED;
4633     output OCLKDIV;
4634     output OSERDESRST;
4635     output [8:0] COUNTERREADVAL;
4636     input COARSEENABLE;
4637     input COARSEINC;
4638     input COUNTERLOADEN;
4639     input COUNTERREADEN;
4640     input DIVIDERST;
4641     input EDGEADV;
4642     input FINEENABLE;
4643     input FINEINC;
4644     input FREQREFCLK;
4645     input MEMREFCLK;
4646     input PHASEREFCLK;
4647     (* invertible_pin = "IS_RST_INVERTED" *)
4648     input RST;
4649     input SELFINEOCLKDELAY;
4650     input SYNCIN;
4651     input SYSCLK;
4652     input [8:0] COUNTERLOADVAL;
4653 endmodule
4654
4655 module PHASER_OUT_PHY (...);
4656     parameter integer CLKOUT_DIV = 4;
4657     parameter COARSE_BYPASS = "FALSE";
4658     parameter integer COARSE_DELAY = 0;
4659     parameter DATA_CTL_N = "FALSE";
4660     parameter DATA_RD_CYCLES = "FALSE";
4661     parameter integer FINE_DELAY = 0;
4662     parameter [0:0] IS_RST_INVERTED = 1'b0;
4663     parameter real MEMREFCLK_PERIOD = 0.000;
4664     parameter OCLKDELAY_INV = "FALSE";
4665     parameter integer OCLK_DELAY = 0;
4666     parameter OUTPUT_CLK_SRC = "PHASE_REF";
4667     parameter real PHASEREFCLK_PERIOD = 0.000;
4668     parameter [2:0] PO = 3'b000;
4669     parameter real REFCLK_PERIOD = 0.000;
4670     parameter SYNC_IN_DIV_RST = "FALSE";
4671     output COARSEOVERFLOW;
4672     output FINEOVERFLOW;
4673     output OCLK;
4674     output OCLKDELAYED;
4675     output OCLKDIV;
4676     output OSERDESRST;
4677     output RDENABLE;
4678     output [1:0] CTSBUS;
4679     output [1:0] DQSBUS;
4680     output [1:0] DTSBUS;
4681     output [8:0] COUNTERREADVAL;
4682     input BURSTPENDINGPHY;
4683     input COARSEENABLE;
4684     input COARSEINC;
4685     input COUNTERLOADEN;
4686     input COUNTERREADEN;
4687     input FINEENABLE;
4688     input FINEINC;
4689     input FREQREFCLK;
4690     input MEMREFCLK;
4691     input PHASEREFCLK;
4692     (* invertible_pin = "IS_RST_INVERTED" *)
4693     input RST;
4694     input SELFINEOCLKDELAY;
4695     input SYNCIN;
4696     input SYSCLK;
4697     input [1:0] ENCALIBPHY;
4698     input [8:0] COUNTERLOADVAL;
4699 endmodule
4700
4701 module PHASER_REF (...);
4702     parameter [0:0] IS_RST_INVERTED = 1'b0;
4703     parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
4704     output LOCKED;
4705     input CLKIN;
4706     (* invertible_pin = "IS_PWRDWN_INVERTED" *)
4707     input PWRDWN;
4708     (* invertible_pin = "IS_RST_INVERTED" *)
4709     input RST;
4710 endmodule
4711
4712 module PHY_CONTROL (...);
4713     parameter integer AO_TOGGLE = 0;
4714     parameter [3:0] AO_WRLVL_EN = 4'b0000;
4715     parameter BURST_MODE = "FALSE";
4716     parameter integer CLK_RATIO = 1;
4717     parameter integer CMD_OFFSET = 0;
4718     parameter integer CO_DURATION = 0;
4719     parameter DATA_CTL_A_N = "FALSE";
4720     parameter DATA_CTL_B_N = "FALSE";
4721     parameter DATA_CTL_C_N = "FALSE";
4722     parameter DATA_CTL_D_N = "FALSE";
4723     parameter DISABLE_SEQ_MATCH = "TRUE";
4724     parameter integer DI_DURATION = 0;
4725     parameter integer DO_DURATION = 0;
4726     parameter integer EVENTS_DELAY = 63;
4727     parameter integer FOUR_WINDOW_CLOCKS = 63;
4728     parameter MULTI_REGION = "FALSE";
4729     parameter PHY_COUNT_ENABLE = "FALSE";
4730     parameter integer RD_CMD_OFFSET_0 = 0;
4731     parameter integer RD_CMD_OFFSET_1 = 00;
4732     parameter integer RD_CMD_OFFSET_2 = 0;
4733     parameter integer RD_CMD_OFFSET_3 = 0;
4734     parameter integer RD_DURATION_0 = 0;
4735     parameter integer RD_DURATION_1 = 0;
4736     parameter integer RD_DURATION_2 = 0;
4737     parameter integer RD_DURATION_3 = 0;
4738     parameter SYNC_MODE = "FALSE";
4739     parameter integer WR_CMD_OFFSET_0 = 0;
4740     parameter integer WR_CMD_OFFSET_1 = 0;
4741     parameter integer WR_CMD_OFFSET_2 = 0;
4742     parameter integer WR_CMD_OFFSET_3 = 0;
4743     parameter integer WR_DURATION_0 = 0;
4744     parameter integer WR_DURATION_1 = 0;
4745     parameter integer WR_DURATION_2 = 0;
4746     parameter integer WR_DURATION_3 = 0;
4747     output PHYCTLALMOSTFULL;
4748     output PHYCTLEMPTY;
4749     output PHYCTLFULL;
4750     output PHYCTLREADY;
4751     output [1:0] INRANKA;
4752     output [1:0] INRANKB;
4753     output [1:0] INRANKC;
4754     output [1:0] INRANKD;
4755     output [1:0] PCENABLECALIB;
4756     output [3:0] AUXOUTPUT;
4757     output [3:0] INBURSTPENDING;
4758     output [3:0] OUTBURSTPENDING;
4759     input MEMREFCLK;
4760     input PHYCLK;
4761     input PHYCTLMSTREMPTY;
4762     input PHYCTLWRENABLE;
4763     input PLLLOCK;
4764     input READCALIBENABLE;
4765     input REFDLLLOCK;
4766     input RESET;
4767     input SYNCIN;
4768     input WRITECALIBENABLE;
4769     input [31:0] PHYCTLWD;
4770 endmodule
4771
4772 module PULLDOWN (...);
4773     output O;
4774 endmodule
4775
4776 module PULLUP (...);
4777     output O;
4778 endmodule
4779
4780 module FIFO18E1 (...);
4781     parameter ALMOST_EMPTY_OFFSET = 13'h0080;
4782     parameter ALMOST_FULL_OFFSET = 13'h0080;
4783     parameter integer DATA_WIDTH = 4;
4784     parameter integer DO_REG = 1;
4785     parameter EN_SYN = "FALSE";
4786     parameter FIFO_MODE = "FIFO18";
4787     parameter FIRST_WORD_FALL_THROUGH = "FALSE";
4788     parameter INIT = 36'h0;
4789     parameter SIM_DEVICE = "VIRTEX6";
4790     parameter SRVAL = 36'h0;
4791     parameter IS_RDCLK_INVERTED = 1'b0;
4792     parameter IS_RDEN_INVERTED = 1'b0;
4793     parameter IS_RSTREG_INVERTED = 1'b0;
4794     parameter IS_RST_INVERTED = 1'b0;
4795     parameter IS_WRCLK_INVERTED = 1'b0;
4796     parameter IS_WREN_INVERTED = 1'b0;
4797     output ALMOSTEMPTY;
4798     output ALMOSTFULL;
4799     output [31:0] DO;
4800     output [3:0] DOP;
4801     output EMPTY;
4802     output FULL;
4803     output [11:0] RDCOUNT;
4804     output RDERR;
4805     output [11:0] WRCOUNT;
4806     output WRERR;
4807     input [31:0] DI;
4808     input [3:0] DIP;
4809     (* clkbuf_sink *)
4810     (* invertible_pin = "IS_RDCLK_INVERTED" *)
4811     input RDCLK;
4812     (* invertible_pin = "IS_RDEN_INVERTED" *)
4813     input RDEN;
4814     input REGCE;
4815     (* invertible_pin = "IS_RST_INVERTED" *)
4816     input RST;
4817     (* invertible_pin = "IS_RSTREG_INVERTED" *)
4818     input RSTREG;
4819     (* clkbuf_sink *)
4820     (* invertible_pin = "IS_WRCLK_INVERTED" *)
4821     input WRCLK;
4822     (* invertible_pin = "IS_WREN_INVERTED" *)
4823     input WREN;
4824 endmodule
4825
4826 module FIFO36E1 (...);
4827     parameter ALMOST_EMPTY_OFFSET = 13'h0080;
4828     parameter ALMOST_FULL_OFFSET = 13'h0080;
4829     parameter integer DATA_WIDTH = 4;
4830     parameter integer DO_REG = 1;
4831     parameter EN_ECC_READ = "FALSE";
4832     parameter EN_ECC_WRITE = "FALSE";
4833     parameter EN_SYN = "FALSE";
4834     parameter FIFO_MODE = "FIFO36";
4835     parameter FIRST_WORD_FALL_THROUGH = "FALSE";
4836     parameter INIT = 72'h0;
4837     parameter SIM_DEVICE = "VIRTEX6";
4838     parameter SRVAL = 72'h0;
4839     parameter IS_RDCLK_INVERTED = 1'b0;
4840     parameter IS_RDEN_INVERTED = 1'b0;
4841     parameter IS_RSTREG_INVERTED = 1'b0;
4842     parameter IS_RST_INVERTED = 1'b0;
4843     parameter IS_WRCLK_INVERTED = 1'b0;
4844     parameter IS_WREN_INVERTED = 1'b0;
4845     output ALMOSTEMPTY;
4846     output ALMOSTFULL;
4847     output DBITERR;
4848     output [63:0] DO;
4849     output [7:0] DOP;
4850     output [7:0] ECCPARITY;
4851     output EMPTY;
4852     output FULL;
4853     output [12:0] RDCOUNT;
4854     output RDERR;
4855     output SBITERR;
4856     output [12:0] WRCOUNT;
4857     output WRERR;
4858     input [63:0] DI;
4859     input [7:0] DIP;
4860     input INJECTDBITERR;
4861     input INJECTSBITERR;
4862     (* clkbuf_sink *)
4863     (* invertible_pin = "IS_RDCLK_INVERTED" *)
4864     input RDCLK;
4865     (* invertible_pin = "IS_RDEN_INVERTED" *)
4866     input RDEN;
4867     input REGCE;
4868     (* invertible_pin = "IS_RST_INVERTED" *)
4869     input RST;
4870     (* invertible_pin = "IS_RSTREG_INVERTED" *)
4871     input RSTREG;
4872     (* clkbuf_sink *)
4873     (* invertible_pin = "IS_WRCLK_INVERTED" *)
4874     input WRCLK;
4875     (* invertible_pin = "IS_WREN_INVERTED" *)
4876     input WREN;
4877 endmodule
4878
4879 module RAM128X1S (...);
4880     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
4881     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
4882     output O;
4883     input A0;
4884     input A1;
4885     input A2;
4886     input A3;
4887     input A4;
4888     input A5;
4889     input A6;
4890     input D;
4891     (* clkbuf_sink *)
4892     (* invertible_pin = "IS_WCLK_INVERTED" *)
4893     input WCLK;
4894     input WE;
4895 endmodule
4896
4897 module RAM256X1S (...);
4898     parameter [255:0] INIT = 256'h0;
4899     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
4900     output O;
4901     input [7:0] A;
4902     input D;
4903     (* clkbuf_sink *)
4904     (* invertible_pin = "IS_WCLK_INVERTED" *)
4905     input WCLK;
4906     input WE;
4907 endmodule
4908
4909 module RAM32M (...);
4910     parameter [63:0] INIT_A = 64'h0000000000000000;
4911     parameter [63:0] INIT_B = 64'h0000000000000000;
4912     parameter [63:0] INIT_C = 64'h0000000000000000;
4913     parameter [63:0] INIT_D = 64'h0000000000000000;
4914     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
4915     output [1:0] DOA;
4916     output [1:0] DOB;
4917     output [1:0] DOC;
4918     output [1:0] DOD;
4919     input [4:0] ADDRA;
4920     input [4:0] ADDRB;
4921     input [4:0] ADDRC;
4922     input [4:0] ADDRD;
4923     input [1:0] DIA;
4924     input [1:0] DIB;
4925     input [1:0] DIC;
4926     input [1:0] DID;
4927     (* clkbuf_sink *)
4928     (* invertible_pin = "IS_WCLK_INVERTED" *)
4929     input WCLK;
4930     input WE;
4931 endmodule
4932
4933 module RAM32X1S (...);
4934     parameter [31:0] INIT = 32'h00000000;
4935     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
4936     output O;
4937     input A0;
4938     input A1;
4939     input A2;
4940     input A3;
4941     input A4;
4942     input D;
4943     (* clkbuf_sink *)
4944     (* invertible_pin = "IS_WCLK_INVERTED" *)
4945     input WCLK;
4946     input WE;
4947 endmodule
4948
4949 module RAM32X1S_1 (...);
4950     parameter [31:0] INIT = 32'h00000000;
4951     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
4952     output O;
4953     input A0;
4954     input A1;
4955     input A2;
4956     input A3;
4957     input A4;
4958     input D;
4959     (* clkbuf_sink *)
4960     (* invertible_pin = "IS_WCLK_INVERTED" *)
4961     input WCLK;
4962     input WE;
4963 endmodule
4964
4965 module RAM32X2S (...);
4966     parameter [31:0] INIT_00 = 32'h00000000;
4967     parameter [31:0] INIT_01 = 32'h00000000;
4968     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
4969     output O0;
4970     output O1;
4971     input A0;
4972     input A1;
4973     input A2;
4974     input A3;
4975     input A4;
4976     input D0;
4977     input D1;
4978     (* clkbuf_sink *)
4979     (* invertible_pin = "IS_WCLK_INVERTED" *)
4980     input WCLK;
4981     input WE;
4982 endmodule
4983
4984 module RAM64M (...);
4985     parameter [63:0] INIT_A = 64'h0000000000000000;
4986     parameter [63:0] INIT_B = 64'h0000000000000000;
4987     parameter [63:0] INIT_C = 64'h0000000000000000;
4988     parameter [63:0] INIT_D = 64'h0000000000000000;
4989     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
4990     output DOA;
4991     output DOB;
4992     output DOC;
4993     output DOD;
4994     input [5:0] ADDRA;
4995     input [5:0] ADDRB;
4996     input [5:0] ADDRC;
4997     input [5:0] ADDRD;
4998     input DIA;
4999     input DIB;
5000     input DIC;
5001     input DID;
5002     (* clkbuf_sink *)
5003     (* invertible_pin = "IS_WCLK_INVERTED" *)
5004     input WCLK;
5005     input WE;
5006 endmodule
5007
5008 module RAM64X1S (...);
5009     parameter [63:0] INIT = 64'h0000000000000000;
5010     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
5011     output O;
5012     input A0;
5013     input A1;
5014     input A2;
5015     input A3;
5016     input A4;
5017     input A5;
5018     input D;
5019     (* clkbuf_sink *)
5020     (* invertible_pin = "IS_WCLK_INVERTED" *)
5021     input WCLK;
5022     input WE;
5023 endmodule
5024
5025 module RAM64X1S_1 (...);
5026     parameter [63:0] INIT = 64'h0000000000000000;
5027     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
5028     output O;
5029     input A0;
5030     input A1;
5031     input A2;
5032     input A3;
5033     input A4;
5034     input A5;
5035     input D;
5036     (* clkbuf_sink *)
5037     (* invertible_pin = "IS_WCLK_INVERTED" *)
5038     input WCLK;
5039     input WE;
5040 endmodule
5041
5042 module RAM64X2S (...);
5043     parameter [63:0] INIT_00 = 64'h0000000000000000;
5044     parameter [63:0] INIT_01 = 64'h0000000000000000;
5045     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
5046     output O0;
5047     output O1;
5048     input A0;
5049     input A1;
5050     input A2;
5051     input A3;
5052     input A4;
5053     input A5;
5054     input D0;
5055     input D1;
5056     (* clkbuf_sink *)
5057     (* invertible_pin = "IS_WCLK_INVERTED" *)
5058     input WCLK;
5059     input WE;
5060 endmodule
5061
5062 module ROM128X1 (...);
5063     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
5064     output O;
5065     input A0;
5066     input A1;
5067     input A2;
5068     input A3;
5069     input A4;
5070     input A5;
5071     input A6;
5072 endmodule
5073
5074 module ROM256X1 (...);
5075     parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
5076     output O;
5077     input A0;
5078     input A1;
5079     input A2;
5080     input A3;
5081     input A4;
5082     input A5;
5083     input A6;
5084     input A7;
5085 endmodule
5086
5087 module ROM32X1 (...);
5088     parameter [31:0] INIT = 32'h00000000;
5089     output O;
5090     input A0;
5091     input A1;
5092     input A2;
5093     input A3;
5094     input A4;
5095 endmodule
5096
5097 module ROM64X1 (...);
5098     parameter [63:0] INIT = 64'h0000000000000000;
5099     output O;
5100     input A0;
5101     input A1;
5102     input A2;
5103     input A3;
5104     input A4;
5105     input A5;
5106 endmodule
5107
5108 module IDDR (...);
5109     parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
5110     parameter INIT_Q1 = 1'b0;
5111     parameter INIT_Q2 = 1'b0;
5112     parameter [0:0] IS_C_INVERTED = 1'b0;
5113     parameter [0:0] IS_D_INVERTED = 1'b0;
5114     parameter SRTYPE = "SYNC";
5115     parameter MSGON = "TRUE";
5116     parameter XON = "TRUE";
5117     output Q1;
5118     output Q2;
5119     (* clkbuf_sink *)
5120     (* invertible_pin = "IS_C_INVERTED" *)
5121     input C;
5122     input CE;
5123     (* invertible_pin = "IS_D_INVERTED" *)
5124     input D;
5125     input R;
5126     input S;
5127 endmodule
5128
5129 module IDDR_2CLK (...);
5130     parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
5131     parameter INIT_Q1 = 1'b0;
5132     parameter INIT_Q2 = 1'b0;
5133     parameter [0:0] IS_CB_INVERTED = 1'b0;
5134     parameter [0:0] IS_C_INVERTED = 1'b0;
5135     parameter [0:0] IS_D_INVERTED = 1'b0;
5136     parameter SRTYPE = "SYNC";
5137     output Q1;
5138     output Q2;
5139     (* clkbuf_sink *)
5140     (* invertible_pin = "IS_C_INVERTED" *)
5141     input C;
5142     (* clkbuf_sink *)
5143     (* invertible_pin = "IS_CB_INVERTED" *)
5144     input CB;
5145     input CE;
5146     (* invertible_pin = "IS_D_INVERTED" *)
5147     input D;
5148     input R;
5149     input S;
5150 endmodule
5151
5152 module ODDR (...);
5153     parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
5154     parameter INIT = 1'b0;
5155     parameter [0:0] IS_C_INVERTED = 1'b0;
5156     parameter [0:0] IS_D1_INVERTED = 1'b0;
5157     parameter [0:0] IS_D2_INVERTED = 1'b0;
5158     parameter SRTYPE = "SYNC";
5159     parameter MSGON = "TRUE";
5160     parameter XON = "TRUE";
5161     output Q;
5162     (* clkbuf_sink *)
5163     (* invertible_pin = "IS_C_INVERTED" *)
5164     input C;
5165     input CE;
5166     (* invertible_pin = "IS_D1_INVERTED" *)
5167     input D1;
5168     (* invertible_pin = "IS_D2_INVERTED" *)
5169     input D2;
5170     input R;
5171     input S;
5172 endmodule
5173
5174 module CFGLUT5 (...);
5175     parameter [31:0] INIT = 32'h00000000;
5176     parameter [0:0] IS_CLK_INVERTED = 1'b0;
5177     output CDO;
5178     output O5;
5179     output O6;
5180     input I4;
5181     input I3;
5182     input I2;
5183     input I1;
5184     input I0;
5185     input CDI;
5186     input CE;
5187     (* clkbuf_sink *)
5188     (* invertible_pin = "IS_CLK_INVERTED" *)
5189     input CLK;
5190 endmodule
5191
5192 (* keep *)
5193 module PS7 (...);
5194     output DMA0DAVALID;
5195     output DMA0DRREADY;
5196     output DMA0RSTN;
5197     output DMA1DAVALID;
5198     output DMA1DRREADY;
5199     output DMA1RSTN;
5200     output DMA2DAVALID;
5201     output DMA2DRREADY;
5202     output DMA2RSTN;
5203     output DMA3DAVALID;
5204     output DMA3DRREADY;
5205     output DMA3RSTN;
5206     output EMIOCAN0PHYTX;
5207     output EMIOCAN1PHYTX;
5208     output EMIOENET0GMIITXEN;
5209     output EMIOENET0GMIITXER;
5210     output EMIOENET0MDIOMDC;
5211     output EMIOENET0MDIOO;
5212     output EMIOENET0MDIOTN;
5213     output EMIOENET0PTPDELAYREQRX;
5214     output EMIOENET0PTPDELAYREQTX;
5215     output EMIOENET0PTPPDELAYREQRX;
5216     output EMIOENET0PTPPDELAYREQTX;
5217     output EMIOENET0PTPPDELAYRESPRX;
5218     output EMIOENET0PTPPDELAYRESPTX;
5219     output EMIOENET0PTPSYNCFRAMERX;
5220     output EMIOENET0PTPSYNCFRAMETX;
5221     output EMIOENET0SOFRX;
5222     output EMIOENET0SOFTX;
5223     output EMIOENET1GMIITXEN;
5224     output EMIOENET1GMIITXER;
5225     output EMIOENET1MDIOMDC;
5226     output EMIOENET1MDIOO;
5227     output EMIOENET1MDIOTN;
5228     output EMIOENET1PTPDELAYREQRX;
5229     output EMIOENET1PTPDELAYREQTX;
5230     output EMIOENET1PTPPDELAYREQRX;
5231     output EMIOENET1PTPPDELAYREQTX;
5232     output EMIOENET1PTPPDELAYRESPRX;
5233     output EMIOENET1PTPPDELAYRESPTX;
5234     output EMIOENET1PTPSYNCFRAMERX;
5235     output EMIOENET1PTPSYNCFRAMETX;
5236     output EMIOENET1SOFRX;
5237     output EMIOENET1SOFTX;
5238     output EMIOI2C0SCLO;
5239     output EMIOI2C0SCLTN;
5240     output EMIOI2C0SDAO;
5241     output EMIOI2C0SDATN;
5242     output EMIOI2C1SCLO;
5243     output EMIOI2C1SCLTN;
5244     output EMIOI2C1SDAO;
5245     output EMIOI2C1SDATN;
5246     output EMIOPJTAGTDO;
5247     output EMIOPJTAGTDTN;
5248     output EMIOSDIO0BUSPOW;
5249     output EMIOSDIO0CLK;
5250     output EMIOSDIO0CMDO;
5251     output EMIOSDIO0CMDTN;
5252     output EMIOSDIO0LED;
5253     output EMIOSDIO1BUSPOW;
5254     output EMIOSDIO1CLK;
5255     output EMIOSDIO1CMDO;
5256     output EMIOSDIO1CMDTN;
5257     output EMIOSDIO1LED;
5258     output EMIOSPI0MO;
5259     output EMIOSPI0MOTN;
5260     output EMIOSPI0SCLKO;
5261     output EMIOSPI0SCLKTN;
5262     output EMIOSPI0SO;
5263     output EMIOSPI0SSNTN;
5264     output EMIOSPI0STN;
5265     output EMIOSPI1MO;
5266     output EMIOSPI1MOTN;
5267     output EMIOSPI1SCLKO;
5268     output EMIOSPI1SCLKTN;
5269     output EMIOSPI1SO;
5270     output EMIOSPI1SSNTN;
5271     output EMIOSPI1STN;
5272     output EMIOTRACECTL;
5273     output EMIOUART0DTRN;
5274     output EMIOUART0RTSN;
5275     output EMIOUART0TX;
5276     output EMIOUART1DTRN;
5277     output EMIOUART1RTSN;
5278     output EMIOUART1TX;
5279     output EMIOUSB0VBUSPWRSELECT;
5280     output EMIOUSB1VBUSPWRSELECT;
5281     output EMIOWDTRSTO;
5282     output EVENTEVENTO;
5283     output MAXIGP0ARESETN;
5284     output MAXIGP0ARVALID;
5285     output MAXIGP0AWVALID;
5286     output MAXIGP0BREADY;
5287     output MAXIGP0RREADY;
5288     output MAXIGP0WLAST;
5289     output MAXIGP0WVALID;
5290     output MAXIGP1ARESETN;
5291     output MAXIGP1ARVALID;
5292     output MAXIGP1AWVALID;
5293     output MAXIGP1BREADY;
5294     output MAXIGP1RREADY;
5295     output MAXIGP1WLAST;
5296     output MAXIGP1WVALID;
5297     output SAXIACPARESETN;
5298     output SAXIACPARREADY;
5299     output SAXIACPAWREADY;
5300     output SAXIACPBVALID;
5301     output SAXIACPRLAST;
5302     output SAXIACPRVALID;
5303     output SAXIACPWREADY;
5304     output SAXIGP0ARESETN;
5305     output SAXIGP0ARREADY;
5306     output SAXIGP0AWREADY;
5307     output SAXIGP0BVALID;
5308     output SAXIGP0RLAST;
5309     output SAXIGP0RVALID;
5310     output SAXIGP0WREADY;
5311     output SAXIGP1ARESETN;
5312     output SAXIGP1ARREADY;
5313     output SAXIGP1AWREADY;
5314     output SAXIGP1BVALID;
5315     output SAXIGP1RLAST;
5316     output SAXIGP1RVALID;
5317     output SAXIGP1WREADY;
5318     output SAXIHP0ARESETN;
5319     output SAXIHP0ARREADY;
5320     output SAXIHP0AWREADY;
5321     output SAXIHP0BVALID;
5322     output SAXIHP0RLAST;
5323     output SAXIHP0RVALID;
5324     output SAXIHP0WREADY;
5325     output SAXIHP1ARESETN;
5326     output SAXIHP1ARREADY;
5327     output SAXIHP1AWREADY;
5328     output SAXIHP1BVALID;
5329     output SAXIHP1RLAST;
5330     output SAXIHP1RVALID;
5331     output SAXIHP1WREADY;
5332     output SAXIHP2ARESETN;
5333     output SAXIHP2ARREADY;
5334     output SAXIHP2AWREADY;
5335     output SAXIHP2BVALID;
5336     output SAXIHP2RLAST;
5337     output SAXIHP2RVALID;
5338     output SAXIHP2WREADY;
5339     output SAXIHP3ARESETN;
5340     output SAXIHP3ARREADY;
5341     output SAXIHP3AWREADY;
5342     output SAXIHP3BVALID;
5343     output SAXIHP3RLAST;
5344     output SAXIHP3RVALID;
5345     output SAXIHP3WREADY;
5346     output [11:0] MAXIGP0ARID;
5347     output [11:0] MAXIGP0AWID;
5348     output [11:0] MAXIGP0WID;
5349     output [11:0] MAXIGP1ARID;
5350     output [11:0] MAXIGP1AWID;
5351     output [11:0] MAXIGP1WID;
5352     output [1:0] DMA0DATYPE;
5353     output [1:0] DMA1DATYPE;
5354     output [1:0] DMA2DATYPE;
5355     output [1:0] DMA3DATYPE;
5356     output [1:0] EMIOUSB0PORTINDCTL;
5357     output [1:0] EMIOUSB1PORTINDCTL;
5358     output [1:0] EVENTSTANDBYWFE;
5359     output [1:0] EVENTSTANDBYWFI;
5360     output [1:0] MAXIGP0ARBURST;
5361     output [1:0] MAXIGP0ARLOCK;
5362     output [1:0] MAXIGP0ARSIZE;
5363     output [1:0] MAXIGP0AWBURST;
5364     output [1:0] MAXIGP0AWLOCK;
5365     output [1:0] MAXIGP0AWSIZE;
5366     output [1:0] MAXIGP1ARBURST;
5367     output [1:0] MAXIGP1ARLOCK;
5368     output [1:0] MAXIGP1ARSIZE;
5369     output [1:0] MAXIGP1AWBURST;
5370     output [1:0] MAXIGP1AWLOCK;
5371     output [1:0] MAXIGP1AWSIZE;
5372     output [1:0] SAXIACPBRESP;
5373     output [1:0] SAXIACPRRESP;
5374     output [1:0] SAXIGP0BRESP;
5375     output [1:0] SAXIGP0RRESP;
5376     output [1:0] SAXIGP1BRESP;
5377     output [1:0] SAXIGP1RRESP;
5378     output [1:0] SAXIHP0BRESP;
5379     output [1:0] SAXIHP0RRESP;
5380     output [1:0] SAXIHP1BRESP;
5381     output [1:0] SAXIHP1RRESP;
5382     output [1:0] SAXIHP2BRESP;
5383     output [1:0] SAXIHP2RRESP;
5384     output [1:0] SAXIHP3BRESP;
5385     output [1:0] SAXIHP3RRESP;
5386     output [28:0] IRQP2F;
5387     output [2:0] EMIOSDIO0BUSVOLT;
5388     output [2:0] EMIOSDIO1BUSVOLT;
5389     output [2:0] EMIOSPI0SSON;
5390     output [2:0] EMIOSPI1SSON;
5391     output [2:0] EMIOTTC0WAVEO;
5392     output [2:0] EMIOTTC1WAVEO;
5393     output [2:0] MAXIGP0ARPROT;
5394     output [2:0] MAXIGP0AWPROT;
5395     output [2:0] MAXIGP1ARPROT;
5396     output [2:0] MAXIGP1AWPROT;
5397     output [2:0] SAXIACPBID;
5398     output [2:0] SAXIACPRID;
5399     output [2:0] SAXIHP0RACOUNT;
5400     output [2:0] SAXIHP1RACOUNT;
5401     output [2:0] SAXIHP2RACOUNT;
5402     output [2:0] SAXIHP3RACOUNT;
5403     output [31:0] EMIOTRACEDATA;
5404     output [31:0] FTMTP2FDEBUG;
5405     output [31:0] MAXIGP0ARADDR;
5406     output [31:0] MAXIGP0AWADDR;
5407     output [31:0] MAXIGP0WDATA;
5408     output [31:0] MAXIGP1ARADDR;
5409     output [31:0] MAXIGP1AWADDR;
5410     output [31:0] MAXIGP1WDATA;
5411     output [31:0] SAXIGP0RDATA;
5412     output [31:0] SAXIGP1RDATA;
5413     output [3:0] EMIOSDIO0DATAO;
5414     output [3:0] EMIOSDIO0DATATN;
5415     output [3:0] EMIOSDIO1DATAO;
5416     output [3:0] EMIOSDIO1DATATN;
5417     output [3:0] FCLKCLK;
5418     output [3:0] FCLKRESETN;
5419     output [3:0] FTMTF2PTRIGACK;
5420     output [3:0] FTMTP2FTRIG;
5421     output [3:0] MAXIGP0ARCACHE;
5422     output [3:0] MAXIGP0ARLEN;
5423     output [3:0] MAXIGP0ARQOS;
5424     output [3:0] MAXIGP0AWCACHE;
5425     output [3:0] MAXIGP0AWLEN;
5426     output [3:0] MAXIGP0AWQOS;
5427     output [3:0] MAXIGP0WSTRB;
5428     output [3:0] MAXIGP1ARCACHE;
5429     output [3:0] MAXIGP1ARLEN;
5430     output [3:0] MAXIGP1ARQOS;
5431     output [3:0] MAXIGP1AWCACHE;
5432     output [3:0] MAXIGP1AWLEN;
5433     output [3:0] MAXIGP1AWQOS;
5434     output [3:0] MAXIGP1WSTRB;
5435     output [5:0] SAXIGP0BID;
5436     output [5:0] SAXIGP0RID;
5437     output [5:0] SAXIGP1BID;
5438     output [5:0] SAXIGP1RID;
5439     output [5:0] SAXIHP0BID;
5440     output [5:0] SAXIHP0RID;
5441     output [5:0] SAXIHP0WACOUNT;
5442     output [5:0] SAXIHP1BID;
5443     output [5:0] SAXIHP1RID;
5444     output [5:0] SAXIHP1WACOUNT;
5445     output [5:0] SAXIHP2BID;
5446     output [5:0] SAXIHP2RID;
5447     output [5:0] SAXIHP2WACOUNT;
5448     output [5:0] SAXIHP3BID;
5449     output [5:0] SAXIHP3RID;
5450     output [5:0] SAXIHP3WACOUNT;
5451     output [63:0] EMIOGPIOO;
5452     output [63:0] EMIOGPIOTN;
5453     output [63:0] SAXIACPRDATA;
5454     output [63:0] SAXIHP0RDATA;
5455     output [63:0] SAXIHP1RDATA;
5456     output [63:0] SAXIHP2RDATA;
5457     output [63:0] SAXIHP3RDATA;
5458     output [7:0] EMIOENET0GMIITXD;
5459     output [7:0] EMIOENET1GMIITXD;
5460     output [7:0] SAXIHP0RCOUNT;
5461     output [7:0] SAXIHP0WCOUNT;
5462     output [7:0] SAXIHP1RCOUNT;
5463     output [7:0] SAXIHP1WCOUNT;
5464     output [7:0] SAXIHP2RCOUNT;
5465     output [7:0] SAXIHP2WCOUNT;
5466     output [7:0] SAXIHP3RCOUNT;
5467     output [7:0] SAXIHP3WCOUNT;
5468     inout DDRCASB;
5469     inout DDRCKE;
5470     inout DDRCKN;
5471     inout DDRCKP;
5472     inout DDRCSB;
5473     inout DDRDRSTB;
5474     inout DDRODT;
5475     inout DDRRASB;
5476     inout DDRVRN;
5477     inout DDRVRP;
5478     inout DDRWEB;
5479     inout PSCLK;
5480     inout PSPORB;
5481     inout PSSRSTB;
5482     inout [14:0] DDRA;
5483     inout [2:0] DDRBA;
5484     inout [31:0] DDRDQ;
5485     inout [3:0] DDRDM;
5486     inout [3:0] DDRDQSN;
5487     inout [3:0] DDRDQSP;
5488     inout [53:0] MIO;
5489     input DMA0ACLK;
5490     input DMA0DAREADY;
5491     input DMA0DRLAST;
5492     input DMA0DRVALID;
5493     input DMA1ACLK;
5494     input DMA1DAREADY;
5495     input DMA1DRLAST;
5496     input DMA1DRVALID;
5497     input DMA2ACLK;
5498     input DMA2DAREADY;
5499     input DMA2DRLAST;
5500     input DMA2DRVALID;
5501     input DMA3ACLK;
5502     input DMA3DAREADY;
5503     input DMA3DRLAST;
5504     input DMA3DRVALID;
5505     input EMIOCAN0PHYRX;
5506     input EMIOCAN1PHYRX;
5507     input EMIOENET0EXTINTIN;
5508     input EMIOENET0GMIICOL;
5509     input EMIOENET0GMIICRS;
5510     input EMIOENET0GMIIRXCLK;
5511     input EMIOENET0GMIIRXDV;
5512     input EMIOENET0GMIIRXER;
5513     input EMIOENET0GMIITXCLK;
5514     input EMIOENET0MDIOI;
5515     input EMIOENET1EXTINTIN;
5516     input EMIOENET1GMIICOL;
5517     input EMIOENET1GMIICRS;
5518     input EMIOENET1GMIIRXCLK;
5519     input EMIOENET1GMIIRXDV;
5520     input EMIOENET1GMIIRXER;
5521     input EMIOENET1GMIITXCLK;
5522     input EMIOENET1MDIOI;
5523     input EMIOI2C0SCLI;
5524     input EMIOI2C0SDAI;
5525     input EMIOI2C1SCLI;
5526     input EMIOI2C1SDAI;
5527     input EMIOPJTAGTCK;
5528     input EMIOPJTAGTDI;
5529     input EMIOPJTAGTMS;
5530     input EMIOSDIO0CDN;
5531     input EMIOSDIO0CLKFB;
5532     input EMIOSDIO0CMDI;
5533     input EMIOSDIO0WP;
5534     input EMIOSDIO1CDN;
5535     input EMIOSDIO1CLKFB;
5536     input EMIOSDIO1CMDI;
5537     input EMIOSDIO1WP;
5538     input EMIOSPI0MI;
5539     input EMIOSPI0SCLKI;
5540     input EMIOSPI0SI;
5541     input EMIOSPI0SSIN;
5542     input EMIOSPI1MI;
5543     input EMIOSPI1SCLKI;
5544     input EMIOSPI1SI;
5545     input EMIOSPI1SSIN;
5546     input EMIOSRAMINTIN;
5547     input EMIOTRACECLK;
5548     input EMIOUART0CTSN;
5549     input EMIOUART0DCDN;
5550     input EMIOUART0DSRN;
5551     input EMIOUART0RIN;
5552     input EMIOUART0RX;
5553     input EMIOUART1CTSN;
5554     input EMIOUART1DCDN;
5555     input EMIOUART1DSRN;
5556     input EMIOUART1RIN;
5557     input EMIOUART1RX;
5558     input EMIOUSB0VBUSPWRFAULT;
5559     input EMIOUSB1VBUSPWRFAULT;
5560     input EMIOWDTCLKI;
5561     input EVENTEVENTI;
5562     input FPGAIDLEN;
5563     input FTMDTRACEINCLOCK;
5564     input FTMDTRACEINVALID;
5565     input MAXIGP0ACLK;
5566     input MAXIGP0ARREADY;
5567     input MAXIGP0AWREADY;
5568     input MAXIGP0BVALID;
5569     input MAXIGP0RLAST;
5570     input MAXIGP0RVALID;
5571     input MAXIGP0WREADY;
5572     input MAXIGP1ACLK;
5573     input MAXIGP1ARREADY;
5574     input MAXIGP1AWREADY;
5575     input MAXIGP1BVALID;
5576     input MAXIGP1RLAST;
5577     input MAXIGP1RVALID;
5578     input MAXIGP1WREADY;
5579     input SAXIACPACLK;
5580     input SAXIACPARVALID;
5581     input SAXIACPAWVALID;
5582     input SAXIACPBREADY;
5583     input SAXIACPRREADY;
5584     input SAXIACPWLAST;
5585     input SAXIACPWVALID;
5586     input SAXIGP0ACLK;
5587     input SAXIGP0ARVALID;
5588     input SAXIGP0AWVALID;
5589     input SAXIGP0BREADY;
5590     input SAXIGP0RREADY;
5591     input SAXIGP0WLAST;
5592     input SAXIGP0WVALID;
5593     input SAXIGP1ACLK;
5594     input SAXIGP1ARVALID;
5595     input SAXIGP1AWVALID;
5596     input SAXIGP1BREADY;
5597     input SAXIGP1RREADY;
5598     input SAXIGP1WLAST;
5599     input SAXIGP1WVALID;
5600     input SAXIHP0ACLK;
5601     input SAXIHP0ARVALID;
5602     input SAXIHP0AWVALID;
5603     input SAXIHP0BREADY;
5604     input SAXIHP0RDISSUECAP1EN;
5605     input SAXIHP0RREADY;
5606     input SAXIHP0WLAST;
5607     input SAXIHP0WRISSUECAP1EN;
5608     input SAXIHP0WVALID;
5609     input SAXIHP1ACLK;
5610     input SAXIHP1ARVALID;
5611     input SAXIHP1AWVALID;
5612     input SAXIHP1BREADY;
5613     input SAXIHP1RDISSUECAP1EN;
5614     input SAXIHP1RREADY;
5615     input SAXIHP1WLAST;
5616     input SAXIHP1WRISSUECAP1EN;
5617     input SAXIHP1WVALID;
5618     input SAXIHP2ACLK;
5619     input SAXIHP2ARVALID;
5620     input SAXIHP2AWVALID;
5621     input SAXIHP2BREADY;
5622     input SAXIHP2RDISSUECAP1EN;
5623     input SAXIHP2RREADY;
5624     input SAXIHP2WLAST;
5625     input SAXIHP2WRISSUECAP1EN;
5626     input SAXIHP2WVALID;
5627     input SAXIHP3ACLK;
5628     input SAXIHP3ARVALID;
5629     input SAXIHP3AWVALID;
5630     input SAXIHP3BREADY;
5631     input SAXIHP3RDISSUECAP1EN;
5632     input SAXIHP3RREADY;
5633     input SAXIHP3WLAST;
5634     input SAXIHP3WRISSUECAP1EN;
5635     input SAXIHP3WVALID;
5636     input [11:0] MAXIGP0BID;
5637     input [11:0] MAXIGP0RID;
5638     input [11:0] MAXIGP1BID;
5639     input [11:0] MAXIGP1RID;
5640     input [19:0] IRQF2P;
5641     input [1:0] DMA0DRTYPE;
5642     input [1:0] DMA1DRTYPE;
5643     input [1:0] DMA2DRTYPE;
5644     input [1:0] DMA3DRTYPE;
5645     input [1:0] MAXIGP0BRESP;
5646     input [1:0] MAXIGP0RRESP;
5647     input [1:0] MAXIGP1BRESP;
5648     input [1:0] MAXIGP1RRESP;
5649     input [1:0] SAXIACPARBURST;
5650     input [1:0] SAXIACPARLOCK;
5651     input [1:0] SAXIACPARSIZE;
5652     input [1:0] SAXIACPAWBURST;
5653     input [1:0] SAXIACPAWLOCK;
5654     input [1:0] SAXIACPAWSIZE;
5655     input [1:0] SAXIGP0ARBURST;
5656     input [1:0] SAXIGP0ARLOCK;
5657     input [1:0] SAXIGP0ARSIZE;
5658     input [1:0] SAXIGP0AWBURST;
5659     input [1:0] SAXIGP0AWLOCK;
5660     input [1:0] SAXIGP0AWSIZE;
5661     input [1:0] SAXIGP1ARBURST;
5662     input [1:0] SAXIGP1ARLOCK;
5663     input [1:0] SAXIGP1ARSIZE;
5664     input [1:0] SAXIGP1AWBURST;
5665     input [1:0] SAXIGP1AWLOCK;
5666     input [1:0] SAXIGP1AWSIZE;
5667     input [1:0] SAXIHP0ARBURST;
5668     input [1:0] SAXIHP0ARLOCK;
5669     input [1:0] SAXIHP0ARSIZE;
5670     input [1:0] SAXIHP0AWBURST;
5671     input [1:0] SAXIHP0AWLOCK;
5672     input [1:0] SAXIHP0AWSIZE;
5673     input [1:0] SAXIHP1ARBURST;
5674     input [1:0] SAXIHP1ARLOCK;
5675     input [1:0] SAXIHP1ARSIZE;
5676     input [1:0] SAXIHP1AWBURST;
5677     input [1:0] SAXIHP1AWLOCK;
5678     input [1:0] SAXIHP1AWSIZE;
5679     input [1:0] SAXIHP2ARBURST;
5680     input [1:0] SAXIHP2ARLOCK;
5681     input [1:0] SAXIHP2ARSIZE;
5682     input [1:0] SAXIHP2AWBURST;
5683     input [1:0] SAXIHP2AWLOCK;
5684     input [1:0] SAXIHP2AWSIZE;
5685     input [1:0] SAXIHP3ARBURST;
5686     input [1:0] SAXIHP3ARLOCK;
5687     input [1:0] SAXIHP3ARSIZE;
5688     input [1:0] SAXIHP3AWBURST;
5689     input [1:0] SAXIHP3AWLOCK;
5690     input [1:0] SAXIHP3AWSIZE;
5691     input [2:0] EMIOTTC0CLKI;
5692     input [2:0] EMIOTTC1CLKI;
5693     input [2:0] SAXIACPARID;
5694     input [2:0] SAXIACPARPROT;
5695     input [2:0] SAXIACPAWID;
5696     input [2:0] SAXIACPAWPROT;
5697     input [2:0] SAXIACPWID;
5698     input [2:0] SAXIGP0ARPROT;
5699     input [2:0] SAXIGP0AWPROT;
5700     input [2:0] SAXIGP1ARPROT;
5701     input [2:0] SAXIGP1AWPROT;
5702     input [2:0] SAXIHP0ARPROT;
5703     input [2:0] SAXIHP0AWPROT;
5704     input [2:0] SAXIHP1ARPROT;
5705     input [2:0] SAXIHP1AWPROT;
5706     input [2:0] SAXIHP2ARPROT;
5707     input [2:0] SAXIHP2AWPROT;
5708     input [2:0] SAXIHP3ARPROT;
5709     input [2:0] SAXIHP3AWPROT;
5710     input [31:0] FTMDTRACEINDATA;
5711     input [31:0] FTMTF2PDEBUG;
5712     input [31:0] MAXIGP0RDATA;
5713     input [31:0] MAXIGP1RDATA;
5714     input [31:0] SAXIACPARADDR;
5715     input [31:0] SAXIACPAWADDR;
5716     input [31:0] SAXIGP0ARADDR;
5717     input [31:0] SAXIGP0AWADDR;
5718     input [31:0] SAXIGP0WDATA;
5719     input [31:0] SAXIGP1ARADDR;
5720     input [31:0] SAXIGP1AWADDR;
5721     input [31:0] SAXIGP1WDATA;
5722     input [31:0] SAXIHP0ARADDR;
5723     input [31:0] SAXIHP0AWADDR;
5724     input [31:0] SAXIHP1ARADDR;
5725     input [31:0] SAXIHP1AWADDR;
5726     input [31:0] SAXIHP2ARADDR;
5727     input [31:0] SAXIHP2AWADDR;
5728     input [31:0] SAXIHP3ARADDR;
5729     input [31:0] SAXIHP3AWADDR;
5730     input [3:0] DDRARB;
5731     input [3:0] EMIOSDIO0DATAI;
5732     input [3:0] EMIOSDIO1DATAI;
5733     input [3:0] FCLKCLKTRIGN;
5734     input [3:0] FTMDTRACEINATID;
5735     input [3:0] FTMTF2PTRIG;
5736     input [3:0] FTMTP2FTRIGACK;
5737     input [3:0] SAXIACPARCACHE;
5738     input [3:0] SAXIACPARLEN;
5739     input [3:0] SAXIACPARQOS;
5740     input [3:0] SAXIACPAWCACHE;
5741     input [3:0] SAXIACPAWLEN;
5742     input [3:0] SAXIACPAWQOS;
5743     input [3:0] SAXIGP0ARCACHE;
5744     input [3:0] SAXIGP0ARLEN;
5745     input [3:0] SAXIGP0ARQOS;
5746     input [3:0] SAXIGP0AWCACHE;
5747     input [3:0] SAXIGP0AWLEN;
5748     input [3:0] SAXIGP0AWQOS;
5749     input [3:0] SAXIGP0WSTRB;
5750     input [3:0] SAXIGP1ARCACHE;
5751     input [3:0] SAXIGP1ARLEN;
5752     input [3:0] SAXIGP1ARQOS;
5753     input [3:0] SAXIGP1AWCACHE;
5754     input [3:0] SAXIGP1AWLEN;
5755     input [3:0] SAXIGP1AWQOS;
5756     input [3:0] SAXIGP1WSTRB;
5757     input [3:0] SAXIHP0ARCACHE;
5758     input [3:0] SAXIHP0ARLEN;
5759     input [3:0] SAXIHP0ARQOS;
5760     input [3:0] SAXIHP0AWCACHE;
5761     input [3:0] SAXIHP0AWLEN;
5762     input [3:0] SAXIHP0AWQOS;
5763     input [3:0] SAXIHP1ARCACHE;
5764     input [3:0] SAXIHP1ARLEN;
5765     input [3:0] SAXIHP1ARQOS;
5766     input [3:0] SAXIHP1AWCACHE;
5767     input [3:0] SAXIHP1AWLEN;
5768     input [3:0] SAXIHP1AWQOS;
5769     input [3:0] SAXIHP2ARCACHE;
5770     input [3:0] SAXIHP2ARLEN;
5771     input [3:0] SAXIHP2ARQOS;
5772     input [3:0] SAXIHP2AWCACHE;
5773     input [3:0] SAXIHP2AWLEN;
5774     input [3:0] SAXIHP2AWQOS;
5775     input [3:0] SAXIHP3ARCACHE;
5776     input [3:0] SAXIHP3ARLEN;
5777     input [3:0] SAXIHP3ARQOS;
5778     input [3:0] SAXIHP3AWCACHE;
5779     input [3:0] SAXIHP3AWLEN;
5780     input [3:0] SAXIHP3AWQOS;
5781     input [4:0] SAXIACPARUSER;
5782     input [4:0] SAXIACPAWUSER;
5783     input [5:0] SAXIGP0ARID;
5784     input [5:0] SAXIGP0AWID;
5785     input [5:0] SAXIGP0WID;
5786     input [5:0] SAXIGP1ARID;
5787     input [5:0] SAXIGP1AWID;
5788     input [5:0] SAXIGP1WID;
5789     input [5:0] SAXIHP0ARID;
5790     input [5:0] SAXIHP0AWID;
5791     input [5:0] SAXIHP0WID;
5792     input [5:0] SAXIHP1ARID;
5793     input [5:0] SAXIHP1AWID;
5794     input [5:0] SAXIHP1WID;
5795     input [5:0] SAXIHP2ARID;
5796     input [5:0] SAXIHP2AWID;
5797     input [5:0] SAXIHP2WID;
5798     input [5:0] SAXIHP3ARID;
5799     input [5:0] SAXIHP3AWID;
5800     input [5:0] SAXIHP3WID;
5801     input [63:0] EMIOGPIOI;
5802     input [63:0] SAXIACPWDATA;
5803     input [63:0] SAXIHP0WDATA;
5804     input [63:0] SAXIHP1WDATA;
5805     input [63:0] SAXIHP2WDATA;
5806     input [63:0] SAXIHP3WDATA;
5807     input [7:0] EMIOENET0GMIIRXD;
5808     input [7:0] EMIOENET1GMIIRXD;
5809     input [7:0] SAXIACPWSTRB;
5810     input [7:0] SAXIHP0WSTRB;
5811     input [7:0] SAXIHP1WSTRB;
5812     input [7:0] SAXIHP2WSTRB;
5813     input [7:0] SAXIHP3WSTRB;
5814 endmodule
5815