techlibs/xilinx/xc7_ff_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // ============================================================================
  21 // FF mapping for Virtex 6, Series 7 and Ultrascale.  These families support
  22 // the following features:
  23 //
  24 // - a CLB flip-flop can be used as a latch or as a flip-flop
  25 // - a CLB flip-flop has the following pins:
  26 //
  27 //   - data input
  28 //   - clock (or gate for latches) (with optional inversion)
  29 //   - clock enable (or gate enable, which is just ANDed with gate — unused by
  30 //     synthesis)
  31 //   - either a set or a reset input, which (for FFs) can be either
  32 //     synchronous or asynchronous (with optional inversion)
  33 //   - data output
  34 //
  35 // - a flip-flop also has an initial value, which is set at device
  36 //   initialization (or whenever GSR is asserted)
  37
  38 `ifndef _NO_FFS
  39
  40 // No reset.
  41
  42 module  \$_DFF_N_   (input D, C, output Q);
  43   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  44   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
  45   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  46 endmodule
  47 module  \$_DFF_P_   (input D, C, output Q);
  48   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  49   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
  50   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  51 endmodule
  52
  53 // No reset, enable.
  54
  55 module  \$_DFFE_NP_ (input D, C, E, output Q);
  56   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  57   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
  58   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  59 endmodule
  60 module  \$_DFFE_PP_ (input D, C, E, output Q);
  61   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  62   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
  63   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  64 endmodule
  65
  66 // Async reset.
  67
  68 module  \$_DFF_NP0_ (input D, C, R, output Q);
  69   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  70   FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
  71   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  72 endmodule
  73 module  \$_DFF_PP0_ (input D, C, R, output Q);
  74   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  75   FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
  76   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  77 endmodule
  78
  79 module  \$_DFF_NP1_ (input D, C, R, output Q);
  80   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  81   FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
  82   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  83 endmodule
  84 module  \$_DFF_PP1_ (input D, C, R, output Q);
  85   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  86   FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
  87   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  88 endmodule
  89
  90 // Async reset, enable.
  91
  92 module  \$__DFFE_NP0 (input D, C, E, R, output Q);
  93   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  94   FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
  95   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  96 endmodule
  97 module  \$__DFFE_PP0 (input D, C, E, R, output Q);
  98   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  99   FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
 100   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 101 endmodule
 102
 103 module  \$__DFFE_NP1 (input D, C, E, R, output Q);
 104   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 105   FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
 106   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 107 endmodule
 108 module  \$__DFFE_PP1 (input D, C, E, R, output Q);
 109   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 110   FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
 111   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 112 endmodule
 113
 114 // Sync reset.
 115
 116 module  \$__DFFS_NP0_ (input D, C, R, output Q);
 117   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 118   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
 119   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 120 endmodule
 121 module  \$__DFFS_PP0_ (input D, C, R, output Q);
 122   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 123   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
 124   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 125 endmodule
 126
 127 module  \$__DFFS_NP1_ (input D, C, R, output Q);
 128   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 129   FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
 130   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 131 endmodule
 132 module  \$__DFFS_PP1_ (input D, C, R, output Q);
 133   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 134   FDSE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
 135   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 136 endmodule
 137
 138 // Sync reset, enable.
 139
 140 module  \$__DFFSE_NP0 (input D, C, E, R, output Q);
 141   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 142   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
 143   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 144 endmodule
 145 module  \$__DFFSE_PP0 (input D, C, E, R, output Q);
 146   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 147   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
 148   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 149 endmodule
 150
 151 module  \$__DFFSE_NP1 (input D, C, E, R, output Q);
 152   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 153   FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
 154   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 155 endmodule
 156 module  \$__DFFSE_PP1 (input D, C, E, R, output Q);
 157   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 158   FDSE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
 159   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 160 endmodule
 161
 162 // Latches (no reset).
 163
 164 module  \$_DLATCH_N_ (input E, D, output Q);
 165   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 166   LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
 167   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 168 endmodule
 169 module  \$_DLATCH_P_ (input E, D, output Q);
 170   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 171   LDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
 172   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 173 endmodule
 174
 175 // Latches with reset (TODO).
 176
 177 `endif
 178