techlibs/xilinx/xc7_ff_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // ============================================================================
  21 // FF mapping for Virtex 6, Series 7 and Ultrascale.  These families support
  22 // the following features:
  23 //
  24 // - a CLB flip-flop can be used as a latch or as a flip-flop
  25 // - a CLB flip-flop has the following pins:
  26 //
  27 //   - data input
  28 //   - clock (or gate for latches) (with optional inversion)
  29 //   - clock enable (or gate enable, which is just ANDed with gate — unused by
  30 //     synthesis)
  31 //   - either a set or a reset input, which (for FFs) can be either
  32 //     synchronous or asynchronous (with optional inversion)
  33 //   - data output
  34 //
  35 // - a flip-flop also has an initial value, which is set at device
  36 //   initialization (or whenever GSR is asserted)
  37
  38 `ifndef _NO_FFS
  39
  40 module  \$_DFF_N_   (input D, C, output Q);
  41   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  42   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
  43   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  44 endmodule
  45 module  \$_DFF_P_   (input D, C, output Q);
  46   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  47   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
  48   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  49 endmodule
  50
  51 module  \$_DFFE_NP_ (input D, C, E, output Q);
  52   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  53   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
  54   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  55 endmodule
  56 module  \$_DFFE_PP_ (input D, C, E, output Q);
  57   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  58   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
  59   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  60 endmodule
  61
  62 module  \$_DFF_NN0_ (input D, C, R, output Q);
  63   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  64   FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
  65   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  66 endmodule
  67 module  \$_DFF_NP0_ (input D, C, R, output Q);
  68   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  69   FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
  70   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  71 endmodule
  72 module  \$_DFF_PN0_ (input D, C, R, output Q);
  73   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  74   FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
  75   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  76 endmodule
  77 module  \$_DFF_PP0_ (input D, C, R, output Q);
  78   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  79   FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
  80   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  81 endmodule
  82
  83 module  \$_DFF_NN1_ (input D, C, R, output Q);
  84   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  85   FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
  86   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  87 endmodule
  88 module  \$_DFF_NP1_ (input D, C, R, output Q);
  89   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  90   FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
  91   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  92 endmodule
  93 module  \$_DFF_PN1_ (input D, C, R, output Q);
  94   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  95   FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
  96   wire _TECHMAP_REMOVEINIT_Q_ = 1;
  97 endmodule
  98 module  \$_DFF_PP1_ (input D, C, R, output Q);
  99   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 100   FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
 101   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 102 endmodule
 103
 104 module  \$_DLATCH_N_ (input E, D, output Q);
 105   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 106   LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
 107   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 108 endmodule
 109 module  \$_DLATCH_P_ (input E, D, output Q);
 110   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
 111   LDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
 112   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 113 endmodule
 114
 115 `endif
 116