techlibs/xilinx/xc7_ff_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // ============================================================================
  21 // FF mapping
  22
  23 `ifndef _NO_FFS
  24
  25 module  \$_DFF_N_   (input D, C, output Q);
  26   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  27   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
  28 endmodule
  29 module  \$_DFF_P_   (input D, C, output Q);
  30   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  31   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
  32 endmodule
  33
  34 module  \$_DFFE_NP_ (input D, C, E, output Q);
  35   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  36   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
  37 endmodule
  38 module  \$_DFFE_PP_ (input D, C, E, output Q);
  39   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  40   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
  41 endmodule
  42
  43 module  \$_DFF_NN0_ (input D, C, R, output Q);
  44   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  45   FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
  46 endmodule
  47 module  \$_DFF_NP0_ (input D, C, R, output Q);
  48   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  49   FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
  50 endmodule
  51 module  \$_DFF_PN0_ (input D, C, R, output Q);
  52   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  53   FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
  54 endmodule
  55 module  \$_DFF_PP0_ (input D, C, R, output Q);
  56   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  57   FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
  58 endmodule
  59
  60 module  \$_DFF_NN1_ (input D, C, R, output Q);
  61   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  62   FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
  63 endmodule
  64 module  \$_DFF_NP1_ (input D, C, R, output Q);
  65   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  66   FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
  67 endmodule
  68 module  \$_DFF_PN1_ (input D, C, R, output Q);
  69   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  70   FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
  71 endmodule
  72 module  \$_DFF_PP1_ (input D, C, R, output Q);
  73   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  74   FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
  75 endmodule
  76
  77 `endif
  78