techlibs/xilinx/xc7_xcu_brams.txt

   1 # Virtex 6, Series 7, Ultrascale, Ultrascale Plus block RAM rules.
   2
   3 bram $__XILINX_RAMB36_SDP
   4   init 1
   5   abits 9
   6   dbits 72
   7   groups 2
   8   ports  1 1
   9   wrmode 0 1
  10   enable 1 8
  11   transp 0 0
  12   clocks 2 3
  13   clkpol 2 3
  14 endbram
  15
  16 bram $__XILINX_RAMB18_SDP
  17   init 1
  18   abits 9
  19   dbits 36
  20   groups 2
  21   ports  1 1
  22   wrmode 0 1
  23   enable 1 4
  24   transp 0 0
  25   clocks 2 3
  26   clkpol 2 3
  27 endbram
  28
  29 bram $__XILINX_RAMB36_TDP
  30   init 1
  31   abits 10     @a10d36
  32   dbits 36     @a10d36
  33   abits 11     @a11d18
  34   dbits 18     @a11d18
  35   abits 12     @a12d9
  36   dbits  9     @a12d9
  37   abits 13     @a13d4
  38   dbits  4     @a13d4
  39   abits 14     @a14d2
  40   dbits  2     @a14d2
  41   abits 15     @a15d1
  42   dbits  1     @a15d1
  43   groups 2
  44   ports  1 1
  45   wrmode 0 1
  46   enable 1 4   @a10d36
  47   enable 1 2   @a11d18
  48   enable 1 1   @a12d9 @a13d4 @a14d2 @a15d1
  49   transp 0 0
  50   clocks 2 3
  51   clkpol 2 3
  52 endbram
  53
  54 bram $__XILINX_RAMB18_TDP
  55   init 1
  56   abits 10     @a10d18
  57   dbits 18     @a10d18
  58   abits 11     @a11d9
  59   dbits  9     @a11d9
  60   abits 12     @a12d4
  61   dbits  4     @a12d4
  62   abits 13     @a13d2
  63   dbits  2     @a13d2
  64   abits 14     @a14d1
  65   dbits  1     @a14d1
  66   groups 2
  67   ports  1 1
  68   wrmode 0 1
  69   enable 1 2   @a10d18
  70   enable 1 1   @a11d9 @a12d4 @a13d2 @a14d1
  71   transp 0 0
  72   clocks 2 3
  73   clkpol 2 3
  74 endbram
  75
  76 # The "min bits" value were taken from:
  77 # [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
  78 # v1.14 ed., p 29-30, July, 2019.
  79 # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
  80
  81 match $__XILINX_RAMB36_SDP
  82   attribute !ram_style
  83   attribute !logic_block
  84   min bits 1024
  85   min efficiency 5
  86   shuffle_enable B
  87   make_transp
  88   or_next_if_better
  89 endmatch
  90
  91 match $__XILINX_RAMB36_SDP
  92   attribute ram_style=block ram_block
  93   attribute !logic_block
  94   shuffle_enable B
  95   make_transp
  96   or_next_if_better
  97 endmatch
  98
  99 match $__XILINX_RAMB18_SDP
 100   attribute !ram_style
 101   attribute !logic_block
 102   min bits 1024
 103   min efficiency 5
 104   shuffle_enable B
 105   make_transp
 106   or_next_if_better
 107 endmatch
 108
 109 match $__XILINX_RAMB18_SDP
 110   attribute ram_style=block ram_block
 111   attribute !logic_block
 112   shuffle_enable B
 113   make_transp
 114   or_next_if_better
 115 endmatch
 116
 117 match $__XILINX_RAMB36_TDP
 118   attribute !ram_style
 119   attribute !logic_block
 120   min bits 1024
 121   min efficiency 5
 122   shuffle_enable B
 123   make_transp
 124   or_next_if_better
 125 endmatch
 126
 127 match $__XILINX_RAMB36_TDP
 128   attribute ram_style=block ram_block
 129   attribute !logic_block
 130   shuffle_enable B
 131   make_transp
 132   or_next_if_better
 133 endmatch
 134
 135 match $__XILINX_RAMB18_TDP
 136   attribute !ram_style
 137   attribute !logic_block
 138   min bits 1024
 139   min efficiency 5
 140   shuffle_enable B
 141   make_transp
 142   or_next_if_better
 143 endmatch
 144
 145 match $__XILINX_RAMB18_TDP
 146   attribute ram_style=block ram_block
 147   attribute !logic_block
 148   shuffle_enable B
 149   make_transp
 150 endmatch
 151