techlibs/xilinx/xc7_xcu_brams.txt

   1 bram $__XILINX_RAMB36_SDP
   2   init 1
   3   abits 9
   4   dbits 72
   5   groups 2
   6   ports  1 1
   7   wrmode 0 1
   8   enable 1 8
   9   transp 0 0
  10   clocks 2 3
  11   clkpol 2 3
  12 endbram
  13
  14 bram $__XILINX_RAMB18_SDP
  15   init 1
  16   abits 9
  17   dbits 36
  18   groups 2
  19   ports  1 1
  20   wrmode 0 1
  21   enable 1 4
  22   transp 0 0
  23   clocks 2 3
  24   clkpol 2 3
  25 endbram
  26
  27 bram $__XILINX_RAMB36_TDP
  28   init 1
  29   abits 10     @a10d36
  30   dbits 36     @a10d36
  31   abits 11     @a11d18
  32   dbits 18     @a11d18
  33   abits 12     @a12d9
  34   dbits  9     @a12d9
  35   abits 13     @a13d4
  36   dbits  4     @a13d4
  37   abits 14     @a14d2
  38   dbits  2     @a14d2
  39   abits 15     @a15d1
  40   dbits  1     @a15d1
  41   groups 2
  42   ports  1 1
  43   wrmode 0 1
  44   enable 1 4   @a10d36
  45   enable 1 2   @a11d18
  46   enable 1 1   @a12d9 @a13d4 @a14d2 @a15d1
  47   transp 0 0
  48   clocks 2 3
  49   clkpol 2 3
  50 endbram
  51
  52 bram $__XILINX_RAMB18_TDP
  53   init 1
  54   abits 10     @a10d18
  55   dbits 18     @a10d18
  56   abits 11     @a11d9
  57   dbits  9     @a11d9
  58   abits 12     @a12d4
  59   dbits  4     @a12d4
  60   abits 13     @a13d2
  61   dbits  2     @a13d2
  62   abits 14     @a14d1
  63   dbits  1     @a14d1
  64   groups 2
  65   ports  1 1
  66   wrmode 0 1
  67   enable 1 2   @a10d18
  68   enable 1 1   @a11d9 @a12d4 @a13d2 @a14d1
  69   transp 0 0
  70   clocks 2 3
  71   clkpol 2 3
  72 endbram
  73
  74 # The "min bits" value were taken from:
  75 # [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
  76 # v1.14 ed., p 29-30, July, 2019.
  77 # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
  78
  79 match $__XILINX_RAMB36_SDP
  80   attribute !ram_style
  81   attribute !logic_block
  82   min bits 1024
  83   min efficiency 5
  84   shuffle_enable B
  85   make_transp
  86   or_next_if_better
  87 endmatch
  88
  89 match $__XILINX_RAMB36_SDP
  90   attribute ram_style=block ram_block
  91   attribute !logic_block
  92   shuffle_enable B
  93   make_transp
  94   or_next_if_better
  95 endmatch
  96
  97 match $__XILINX_RAMB18_SDP
  98   attribute !ram_style
  99   attribute !logic_block
 100   min bits 1024
 101   min efficiency 5
 102   shuffle_enable B
 103   make_transp
 104   or_next_if_better
 105 endmatch
 106
 107 match $__XILINX_RAMB18_SDP
 108   attribute ram_style=block ram_block
 109   attribute !logic_block
 110   shuffle_enable B
 111   make_transp
 112   or_next_if_better
 113 endmatch
 114
 115 match $__XILINX_RAMB36_TDP
 116   attribute !ram_style
 117   attribute !logic_block
 118   min bits 1024
 119   min efficiency 5
 120   shuffle_enable B
 121   make_transp
 122   or_next_if_better
 123 endmatch
 124
 125 match $__XILINX_RAMB36_TDP
 126   attribute ram_style=block ram_block
 127   attribute !logic_block
 128   shuffle_enable B
 129   make_transp
 130   or_next_if_better
 131 endmatch
 132
 133 match $__XILINX_RAMB18_TDP
 134   attribute !ram_style
 135   attribute !logic_block
 136   min bits 1024
 137   min efficiency 5
 138   shuffle_enable B
 139   make_transp
 140   or_next_if_better
 141 endmatch
 142
 143 match $__XILINX_RAMB18_TDP
 144   attribute ram_style=block ram_block
 145   attribute !logic_block
 146   shuffle_enable B
 147   make_transp
 148 endmatch
 149