1 bram $__XILINX_RAMB36_SDP
14 bram $__XILINX_RAMB18_SDP
27 bram $__XILINX_RAMB36_TDP
46 enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1
52 bram $__XILINX_RAMB18_TDP
68 enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
74 # The "min bits" value were taken from:
75 # [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
76 # v1.14 ed., p 29-30, July, 2019.
77 # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
79 match $__XILINX_RAMB36_SDP
81 attribute !logic_block
89 match $__XILINX_RAMB36_SDP
90 attribute ram_style=block ram_block
91 attribute !logic_block
97 match $__XILINX_RAMB18_SDP
99 attribute !logic_block
107 match $__XILINX_RAMB18_SDP
108 attribute ram_style=block ram_block
109 attribute !logic_block
115 match $__XILINX_RAMB36_TDP
117 attribute !logic_block
125 match $__XILINX_RAMB36_TDP
126 attribute ram_style=block ram_block
127 attribute !logic_block
133 match $__XILINX_RAMB18_TDP
135 attribute !logic_block
143 match $__XILINX_RAMB18_TDP
144 attribute ram_style=block ram_block
145 attribute !logic_block