techlibs/xilinx/xcu_brams_map.v

   1 // Ultrascale and Ultrascale Plus block RAM mapping.
   2
   3 module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
   4         parameter CLKPOL2 = 1;
   5         parameter CLKPOL3 = 1;
   6         parameter [36863:0] INIT = 36864'bx;
   7
   8         input CLK2;
   9         input CLK3;
  10
  11         input [8:0] A1ADDR;
  12         output [71:0] A1DATA;
  13         input A1EN;
  14
  15         input [8:0] B1ADDR;
  16         input [71:0] B1DATA;
  17         input [7:0] B1EN;
  18
  19         wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
  20         wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
  21
  22         wire [7:0] DIP, DOP;
  23         wire [63:0] DI, DO;
  24
  25         assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
  26                           DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
  27
  28         assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
  29                  DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
  30
  31         RAMB36E2 #(
  32                 .READ_WIDTH_A(72),
  33                 .WRITE_WIDTH_B(72),
  34                 .WRITE_MODE_A("READ_FIRST"),
  35                 .WRITE_MODE_B("READ_FIRST"),
  36                 .DOA_REG(0),
  37                 .DOB_REG(0),
  38                 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
  39                 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
  40                 `include "brams_init_36.vh"
  41         ) _TECHMAP_REPLACE_ (
  42                 .DOUTBDOUT(DO[63:32]),
  43                 .DOUTADOUT(DO[31:0]),
  44                 .DOUTPBDOUTP(DOP[7:4]),
  45                 .DOUTPADOUTP(DOP[3:0]),
  46                 .DINBDIN(DI[63:32]),
  47                 .DINADIN(DI[31:0]),
  48                 .DINPBDINP(DIP[7:4]),
  49                 .DINPADINP(DIP[3:0]),
  50
  51                 .ADDRARDADDR(A1ADDR_16),
  52                 .CLKARDCLK(CLK2),
  53                 .ENARDEN(A1EN),
  54                 .ADDRENA(|1),
  55                 .REGCEAREGCE(|1),
  56                 .RSTRAMARSTRAM(|0),
  57                 .RSTREGARSTREG(|0),
  58                 .WEA(4'b0),
  59
  60                 .ADDRBWRADDR(B1ADDR_16),
  61                 .CLKBWRCLK(CLK3),
  62                 .ENBWREN(|1),
  63                 .ADDRENB(|1),
  64                 .REGCEB(|1),
  65                 .RSTRAMB(|0),
  66                 .RSTREGB(|0),
  67                 .WEBWE(B1EN),
  68
  69                 .SLEEP(|0)
  70         );
  71 endmodule
  72
  73 // ------------------------------------------------------------------------
  74
  75 module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
  76         parameter CLKPOL2 = 1;
  77         parameter CLKPOL3 = 1;
  78         parameter [18431:0] INIT = 18432'bx;
  79
  80         input CLK2;
  81         input CLK3;
  82
  83         input [8:0] A1ADDR;
  84         output [35:0] A1DATA;
  85         input A1EN;
  86
  87         input [8:0] B1ADDR;
  88         input [35:0] B1DATA;
  89         input [3:0] B1EN;
  90
  91         wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
  92         wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
  93
  94         wire [3:0] DIP, DOP;
  95         wire [31:0] DI, DO;
  96
  97         assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
  98         assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
  99
 100         RAMB18E2 #(
 101                 .READ_WIDTH_A(36),
 102                 .WRITE_WIDTH_B(36),
 103                 .WRITE_MODE_A("READ_FIRST"),
 104                 .WRITE_MODE_B("READ_FIRST"),
 105                 .DOA_REG(0),
 106                 .DOB_REG(0),
 107                 .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 108                 .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 109                 `include "brams_init_18.vh"
 110         ) _TECHMAP_REPLACE_ (
 111                 .DOUTBDOUT(DO[31:16]),
 112                 .DOUTADOUT(DO[15:0]),
 113                 .DOUTPBDOUTP(DOP[3:2]),
 114                 .DOUTPADOUTP(DOP[1:0]),
 115                 .DINBDIN(DI[31:16]),
 116                 .DINADIN(DI[15:0]),
 117                 .DINPBDINP(DIP[3:2]),
 118                 .DINPADINP(DIP[1:0]),
 119
 120                 .ADDRARDADDR(A1ADDR_14),
 121                 .CLKARDCLK(CLK2),
 122                 .ENARDEN(A1EN),
 123                 .ADDRENA(|1),
 124                 .REGCEAREGCE(|1),
 125                 .RSTRAMARSTRAM(|0),
 126                 .RSTREGARSTREG(|0),
 127                 .WEA(2'b0),
 128
 129                 .ADDRBWRADDR(B1ADDR_14),
 130                 .CLKBWRCLK(CLK3),
 131                 .ENBWREN(|1),
 132                 .ADDRENB(|1),
 133                 .REGCEB(|1),
 134                 .RSTRAMB(|0),
 135                 .RSTREGB(|0),
 136                 .WEBWE(B1EN),
 137
 138                 .SLEEP(|0)
 139         );
 140 endmodule
 141
 142 // ------------------------------------------------------------------------
 143
 144 module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 145         parameter CFG_ABITS = 10;
 146         parameter CFG_DBITS = 36;
 147         parameter CFG_ENABLE_B = 4;
 148
 149         parameter CLKPOL2 = 1;
 150         parameter CLKPOL3 = 1;
 151         parameter [36863:0] INIT = 36864'bx;
 152
 153         input CLK2;
 154         input CLK3;
 155
 156         input [CFG_ABITS-1:0] A1ADDR;
 157         output [CFG_DBITS-1:0] A1DATA;
 158         input A1EN;
 159
 160         input [CFG_ABITS-1:0] B1ADDR;
 161         input [CFG_DBITS-1:0] B1DATA;
 162         input [CFG_ENABLE_B-1:0] B1EN;
 163
 164         wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
 165         wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
 166         wire [7:0] B1EN_8 = B1EN;
 167
 168         wire [3:0] DIP, DOP;
 169         wire [31:0] DI, DO;
 170
 171         wire [31:0] DOBDO;
 172         wire [3:0] DOPBDOP;
 173
 174         assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
 175         assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
 176
 177         generate if (CFG_DBITS > 8) begin
 178                 RAMB36E2 #(
 179                         .READ_WIDTH_A(CFG_DBITS),
 180                         .READ_WIDTH_B(CFG_DBITS),
 181                         .WRITE_WIDTH_A(CFG_DBITS),
 182                         .WRITE_WIDTH_B(CFG_DBITS),
 183                         .WRITE_MODE_A("READ_FIRST"),
 184                         .WRITE_MODE_B("READ_FIRST"),
 185                         .DOA_REG(0),
 186                         .DOB_REG(0),
 187                         .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 188                         .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 189                         `include "brams_init_36.vh"
 190                 ) _TECHMAP_REPLACE_ (
 191                         .DINADIN(32'hFFFFFFFF),
 192                         .DINPADINP(4'hF),
 193                         .DOUTADOUT(DO[31:0]),
 194                         .DOUTPADOUTP(DOP[3:0]),
 195                         .ADDRARDADDR(A1ADDR_16),
 196                         .CLKARDCLK(CLK2),
 197                         .ENARDEN(A1EN),
 198                         .ADDRENA(|1),
 199                         .REGCEAREGCE(|1),
 200                         .RSTRAMARSTRAM(|0),
 201                         .RSTREGARSTREG(|0),
 202                         .WEA(4'b0),
 203
 204                         .DINBDIN(DI),
 205                         .DINPBDINP(DIP),
 206                         .DOUTBDOUT(DOBDO),
 207                         .DOUTPBDOUTP(DOPBDOP),
 208                         .ADDRBWRADDR(B1ADDR_16),
 209                         .CLKBWRCLK(CLK3),
 210                         .ENBWREN(|1),
 211                         .ADDRENB(|1),
 212                         .REGCEB(|0),
 213                         .RSTRAMB(|0),
 214                         .RSTREGB(|0),
 215                         .WEBWE(B1EN_8),
 216
 217                         .SLEEP(|0)
 218                 );
 219         end else begin
 220                 RAMB36E2 #(
 221                         .READ_WIDTH_A(CFG_DBITS),
 222                         .READ_WIDTH_B(CFG_DBITS),
 223                         .WRITE_WIDTH_A(CFG_DBITS),
 224                         .WRITE_WIDTH_B(CFG_DBITS),
 225                         .WRITE_MODE_A("READ_FIRST"),
 226                         .WRITE_MODE_B("READ_FIRST"),
 227                         .DOA_REG(0),
 228                         .DOB_REG(0),
 229                         .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 230                         .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 231                         `include "brams_init_32.vh"
 232                 ) _TECHMAP_REPLACE_ (
 233                         .DINADIN(32'hFFFFFFFF),
 234                         .DINPADINP(4'hF),
 235                         .DOUTADOUT(DO[31:0]),
 236                         .DOUTPADOUTP(DOP[3:0]),
 237                         .ADDRARDADDR(A1ADDR_16),
 238                         .CLKARDCLK(CLK2),
 239                         .ENARDEN(A1EN),
 240                         .ADDRENA(|1),
 241                         .REGCEAREGCE(|1),
 242                         .RSTRAMARSTRAM(|0),
 243                         .RSTREGARSTREG(|0),
 244                         .WEA(4'b0),
 245
 246                         .DINBDIN(DI),
 247                         .DINPBDINP(DIP),
 248                         .DOUTBDOUT(DOBDO),
 249                         .DOUTPBDOUTP(DOPBDOP),
 250                         .ADDRBWRADDR(B1ADDR_16),
 251                         .CLKBWRCLK(CLK3),
 252                         .ENBWREN(|1),
 253                         .ADDRENB(|1),
 254                         .REGCEB(|0),
 255                         .RSTRAMB(|0),
 256                         .RSTREGB(|0),
 257                         .WEBWE(B1EN_8),
 258
 259                         .SLEEP(|0)
 260                 );
 261         end endgenerate
 262 endmodule
 263
 264 // ------------------------------------------------------------------------
 265
 266 module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 267         parameter CFG_ABITS = 10;
 268         parameter CFG_DBITS = 18;
 269         parameter CFG_ENABLE_B = 2;
 270
 271         parameter CLKPOL2 = 1;
 272         parameter CLKPOL3 = 1;
 273         parameter [18431:0] INIT = 18432'bx;
 274
 275         input CLK2;
 276         input CLK3;
 277
 278         input [CFG_ABITS-1:0] A1ADDR;
 279         output [CFG_DBITS-1:0] A1DATA;
 280         input A1EN;
 281
 282         input [CFG_ABITS-1:0] B1ADDR;
 283         input [CFG_DBITS-1:0] B1DATA;
 284         input [CFG_ENABLE_B-1:0] B1EN;
 285
 286         wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
 287         wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
 288         wire [3:0] B1EN_4 = B1EN;
 289
 290         wire [1:0] DIP, DOP;
 291         wire [15:0] DI, DO;
 292
 293         wire [15:0] DOBDO;
 294         wire [1:0] DOPBDOP;
 295
 296         assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
 297         assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
 298
 299         generate if (CFG_DBITS > 8) begin
 300                 RAMB18E2 #(
 301                         .READ_WIDTH_A(CFG_DBITS),
 302                         .READ_WIDTH_B(CFG_DBITS),
 303                         .WRITE_WIDTH_A(CFG_DBITS),
 304                         .WRITE_WIDTH_B(CFG_DBITS),
 305                         .WRITE_MODE_A("READ_FIRST"),
 306                         .WRITE_MODE_B("READ_FIRST"),
 307                         .DOA_REG(0),
 308                         .DOB_REG(0),
 309                         .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 310                         .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 311                         `include "brams_init_18.vh"
 312                 ) _TECHMAP_REPLACE_ (
 313                         .DINADIN(16'hFFFF),
 314                         .DINPADINP(2'b11),
 315                         .DOUTADOUT(DO),
 316                         .DOUTPADOUTP(DOP),
 317                         .ADDRARDADDR(A1ADDR_14),
 318                         .CLKARDCLK(CLK2),
 319                         .ENARDEN(A1EN),
 320                         .ADDRENA(|1),
 321                         .REGCEAREGCE(|1),
 322                         .RSTRAMARSTRAM(|0),
 323                         .RSTREGARSTREG(|0),
 324                         .WEA(2'b0),
 325
 326                         .DINBDIN(DI),
 327                         .DINPBDINP(DIP),
 328                         .DOUTBDOUT(DOBDO),
 329                         .DOUTPBDOUTP(DOPBDOP),
 330                         .ADDRBWRADDR(B1ADDR_14),
 331                         .CLKBWRCLK(CLK3),
 332                         .ENBWREN(|1),
 333                         .ADDRENB(|1),
 334                         .REGCEB(|0),
 335                         .RSTRAMB(|0),
 336                         .RSTREGB(|0),
 337                         .WEBWE(B1EN_4),
 338
 339                         .SLEEP(|0)
 340                 );
 341         end else begin
 342                 RAMB18E2 #(
 343                         //.RAM_MODE("TDP"),
 344                         .READ_WIDTH_A(CFG_DBITS),
 345                         .READ_WIDTH_B(CFG_DBITS),
 346                         .WRITE_WIDTH_A(CFG_DBITS),
 347                         .WRITE_WIDTH_B(CFG_DBITS),
 348                         .WRITE_MODE_A("READ_FIRST"),
 349                         .WRITE_MODE_B("READ_FIRST"),
 350                         .DOA_REG(0),
 351                         .DOB_REG(0),
 352                         .IS_CLKARDCLK_INVERTED(!CLKPOL2),
 353                         .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 354                         `include "brams_init_16.vh"
 355                 ) _TECHMAP_REPLACE_ (
 356                         .DINADIN(16'hFFFF),
 357                         .DINPADINP(2'b11),
 358                         .DOUTADOUT(DO),
 359                         .DOUTPADOUTP(DOP),
 360                         .ADDRARDADDR(A1ADDR_14),
 361                         .CLKARDCLK(CLK2),
 362                         .ENARDEN(A1EN),
 363                         .ADDRENA(|1),
 364                         .REGCEAREGCE(|1),
 365                         .RSTRAMARSTRAM(|0),
 366                         .RSTREGARSTREG(|0),
 367                         .WEA(2'b0),
 368
 369                         .DINBDIN(DI),
 370                         .DINPBDINP(DIP),
 371                         .DOUTBDOUT(DOBDO),
 372                         .DOUTPBDOUTP(DOPBDOP),
 373                         .ADDRBWRADDR(B1ADDR_14),
 374                         .CLKBWRCLK(CLK3),
 375                         .ENBWREN(|1),
 376                         .ADDRENB(|1),
 377                         .REGCEB(|0),
 378                         .RSTRAMB(|0),
 379                         .RSTREGB(|0),
 380                         .WEBWE(B1EN_4),
 381
 382                         .SLEEP(|0)
 383                 );
 384         end endgenerate
 385 endmodule
 386