techlibs/xilinx/xilinx_finalise.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *            (C) 2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include "kernel/register.h"
  22 #include "kernel/celltypes.h"
  23 #include "kernel/rtlil.h"
  24 #include "kernel/log.h"
  25
  26 USING_YOSYS_NAMESPACE
  27 PRIVATE_NAMESPACE_BEGIN
  28
  29 struct XilinxFinalisePass : public Pass
  30 {
  31         XilinxFinalisePass() : Pass("xilinx_finalise", "") { }
  32
  33         void help() YS_OVERRIDE
  34         {
  35                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  36                 log("\n");
  37                 log("    xilinx_finalise [options]\n");
  38                 log("\n");
  39         }
  40
  41         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  42         {
  43                 size_t argidx;
  44                 for (argidx = 1; argidx < args.size(); argidx++)
  45                 {
  46                         break;
  47                 }
  48                 extra_args(args, argidx, design);
  49
  50                 log_header(design, "Executing XILINX_FINALISE pass.\n");
  51
  52                 for (auto module : design->selected_modules())
  53                 for (auto cell : module->selected_cells()) {
  54                         if (cell->type != ID(DSP48E1))
  55                                 continue;
  56                         for (auto &conn : cell->connections_) {
  57                                 if (!cell->output(conn.first))
  58                                         continue;
  59                                 bool purge = true;
  60                                 for (auto &chunk : conn.second.chunks()) {
  61                                         auto it = chunk.wire->attributes.find(ID(unused_bits));
  62                                         if (it == chunk.wire->attributes.end())
  63                                                 continue;
  64
  65                                         std::string unused_bits = stringf("%d", chunk.offset);
  66                                         for (auto i = 1; i < chunk.width; i++)
  67                                                 unused_bits += stringf(" %d", i+chunk.offset);
  68
  69                                         if (it->second.decode_string().find(unused_bits) == std::string::npos) {
  70                                                 purge = false;
  71                                                 break;
  72                                         }
  73                                 }
  74
  75                                 if (purge) {
  76                                         log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second));
  77                                         conn.second = SigSpec();
  78                                 }
  79                         }
  80                 }
  81         }
  82 } XilinxFinalisePass;
  83
  84 PRIVATE_NAMESPACE_END