test/test_axi_lite.py

   1 import unittest
   2
   3 from migen import *
   4
   5 from litex.soc.interconnect import csr
   6 from litex.soc.interconnect import csr_bus
   7 from litex.soc.interconnect import axi_lite
   8
   9 class CSRModule(Module, csr.AutoCSR):
  10     def __init__(self):
  11         self.foo = csr.CSRStorage(32, reset=1)
  12         self.bar = csr.CSRStorage(32, reset=1)
  13
  14
  15 class AXILiteDUT(Module):
  16     def __init__(self):
  17         self.csr = csr_bus.Interface(data_width=32, address_width=12)
  18         self.axi = axi_lite.Interface(data_width=32, address_width=14)
  19         self.submodules.csrmodule = CSRModule()
  20         self.submodules.dut = axi_lite.AXILite2CSR(self.axi, self.csr)
  21         self.submodules.csrbankarray = csr_bus.CSRBankArray(
  22             self, self.map_csr, data_width=32, address_width=12)
  23         self.submodules.csrcon = csr_bus.Interconnect(
  24             self.csr, self.csrbankarray.get_buses())
  25
  26     def map_csr(self, name, memory):
  27         return {"csrmodule": 0}[name]
  28
  29
  30 class TestAXILite(unittest.TestCase):
  31     def test_write_read(self):
  32         def generator(dut):
  33             axi = dut.axi
  34
  35             for _ in range(8):
  36                 yield
  37
  38             # Write test
  39             yield axi.aw.valid.eq(1)
  40             yield axi.aw.addr.eq(4)
  41             yield axi.w.valid.eq(1)
  42             yield axi.b.ready.eq(1)
  43             yield axi.w.data.eq(0x2137)
  44
  45             while (yield axi.aw.ready) != 1:
  46                 yield
  47             while (yield axi.w.ready) != 1:
  48                 yield
  49             yield axi.aw.valid.eq(0)
  50             yield axi.w.valid.eq(0)
  51
  52             for _ in range(8):
  53                 yield
  54
  55             # Read test
  56             yield axi.ar.valid.eq(1)
  57             yield axi.r.ready.eq(1)
  58             yield axi.ar.addr.eq(4)
  59
  60             while (yield axi.ar.ready != 1):
  61                 yield
  62             yield axi.ar.valid.eq(0)
  63             while (yield axi.r.valid != 1):
  64                 yield
  65             yield axi.r.ready.eq(0)
  66
  67             read = yield axi.r.data
  68             assert read == 0x2137
  69
  70             for _ in range(8):
  71                 yield
  72         dut = AXILiteDUT()
  73         run_simulation(dut, generator(dut.dut), vcd_name='axi-write-read.vcd')
  74
  75     def test_simultaneous(dut):
  76         def generator(dut):
  77             axi = dut.axi
  78
  79             for _ in range(8):
  80                 yield
  81
  82             # Write
  83             yield axi.aw.valid.eq(1)
  84             yield axi.aw.addr.eq(2)
  85             yield axi.w.valid.eq(1)
  86             yield axi.b.ready.eq(1)
  87             yield axi.w.data.eq(0x2137)
  88             # Read
  89             yield axi.ar.valid.eq(1)
  90             yield axi.r.ready.eq(1)
  91             yield axi.ar.addr.eq(2)
  92
  93             yield
  94             yield
  95
  96             is_reading = yield axi.ar.ready
  97             is_writing = yield axi.aw.ready
  98
  99             assert is_reading
 100             assert not is_writing
 101
 102
 103         dut = AXILiteDUT()
 104         run_simulation(dut, generator(dut.dut), vcd_name='axi-simultaneous.vcd')