loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 107.out
1 GPR0 0000000080000000
2 GPR1 0000000000FC867C
3 GPR2 0000000000000020
4 GPR3 0000000000000000
5 GPR4 00000000FFFFFFFF
6 GPR5 FFFFFFFFFFFFFFFF
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 FFFFFFFEFFFFFFFF
10 GPR9 FFFFFFFFFFFE3FE0
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 FFFFFFFFFFFFFFFE
15 GPR14 FFFFFFFFFFFFFF00
16 GPR15 0000000000000000
17 GPR16 000000000001C020
18 GPR17 0000000000000020
19 GPR18 FFFFFFFFFFFE3FE0
20 GPR19 0000000000000020
21 GPR20 FFFFFFFFFFFFFFFF
22 GPR21 00000007FFFFF000
23 GPR22 000000000001CF06
24 GPR23 000000000001C020
25 GPR24 0000000000000020
26 GPR25 FFFFFFFFFFFE30FA
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0011B141B629DF63
30 GPR29 0000000000000020
31 GPR30 FFFFFFFFFFFFFFFF
32 GPR31
33 CR 000000005FF37D44
34 LR FFFFFFFFFFFE3FE0
35 CTR FFFFFFFFFFFFFFFF
36 XER 00000000A007FFFF
37