loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 111.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 0000000000000000
3 GPR2 000000000001C020
4 GPR3 0000000000000000
5 GPR4 00000000FFFFD42C
6 GPR5 0000000000000000
7 GPR6 FFFFFFFFFFFFFFFF
8 GPR7 0000000000000004
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 FFFFFFFFFFFFD42B
12 GPR11 0000000000000000
13 GPR12 000000000001C020
14 GPR13 0000000000000000
15 GPR14 0000000000000001
16 GPR15 FFFFFFFFFFFFA2CA
17 GPR16 0000000000000000
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFA2CA
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 FFFFFFFFFFFFFFFF
27 GPR26 0000000000000000
28 GPR27 0000000000000040
29 GPR28 FFFFFFFFFFFFEDA2
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 000000009958299B
34 LR FFFFFFFFFFFFFFFF
35 CTR 0000000000000000
36 XER 00000000A0040000
37