loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 149.out
1 GPR0 0000000000000040
2 GPR1 000000000001C020
3 GPR2 0000000000000005
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 FFFFFFFFFFFE3FDF
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 FFFFFFFFFFFE3FCE
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 000000000000700C
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 FFFFFFFFFFFFFFFE
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000004C3B
29 GPR28 0000000000000000
30 GPR29 FFFFFFFFFFFFFFFF
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000030350950
34 LR 0200000002000000
35 CTR FFFFFFFFFFFFDCE5
36 XER 00000000A005C020
37