loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 151.out
1 GPR0 FFFFFFFFFFFFFFFD
2 GPR1 FFFFC00000000000
3 GPR2 0000000000000000
4 GPR3 FFFFFFFFFFFFFFE6
5 GPR4 0000C1FFFC000000
6 GPR5 FFFFC00000000000
7 GPR6 FFFFFFFFFFFFFFFE
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 000000000000000C
13 GPR12 0000000000000000
14 GPR13 000000000000003E
15 GPR14 0000000000000000
16 GPR15 FFFFBFFFFFFE3FE0
17 GPR16 0000000000000000
18 GPR17 00000000FFFFFFFF
19 GPR18 FFFFFFFFFFFFFFEE
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 000000000000000C
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 FFFFC0000000000C
26 GPR25 FFFFFFFFFFFFFFFF
27 GPR26 FFFFFFFFFFFFFFE0
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000015555555
32 GPR31
33 CR 0000000050995593
34 LR 0000000000000000
35 CTR 00000000FFFFFFFF
36 XER 00000000A0040000
37