loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 158.out
1 GPR0 0000000000001B2E
2 GPR1 000000000001C020
3 GPR2 0000000000000000
4 GPR3 FFFFFFFFFFFFFFFF
5 GPR4 0000000000000000
6 GPR5 FFFFFFFFFFFFFFE0
7 GPR6 0000000087810000
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFE3FDF
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 000000000001C020
13 GPR12 0000000000000000
14 GPR13 0000000000000E00
15 GPR14 FFFFFFFFFFFFFE3C
16 GPR15 0000000000000000
17 GPR16 FFFFFFFFFFFE3FE0
18 GPR17 0000000000000000
19 GPR18 0000000000001B0E
20 GPR19 FFFFFFFFFFFFFDFB
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFFFFFFFFF
28 GPR27 0000000000000000
29 GPR28 000000000001C01F
30 GPR29 00000000FFFFFFC0
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000039422355
34 LR 0000000000000000
35 CTR 000000000001C020
36 XER 0000000080000000
37