loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 163.out
1 GPR0 0000000000000000
2 GPR1 0000000000000000
3 GPR2 FFFFFFFFFFFF9A5E
4 GPR3 0000000000000000
5 GPR4 0000000000003127
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 00000000762E0000
9 GPR8 0000000000006978
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFFFFF9A5E
14 GPR13 FFFFFFFFFFFFFFFF
15 GPR14 0000000000000000
16 GPR15 000000000001C020
17 GPR16 0000000000000001
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 000000000001C028
25 GPR24 00000000762E0000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 FFFFFFFFFFFFFFFF
29 GPR28 0000000000005FEC
30 GPR29 0000000000000000
31 GPR30 0000000000000009
32 GPR31
33 CR 0000000053000039
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000080000000
37