loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 167.out
1 GPR0 FFFFFFFFFFFE3FDE
2 GPR1 0000000000000004
3 GPR2 000000000001C021
4 GPR3 0000000000000000
5 GPR4 00000000A0040001
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 000000000001C020
11 GPR10 FFFFFFFFFFFFFFFF
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 000000000000307D
18 GPR17 000000000001C020
19 GPR18 00000000A0040000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 000000000001C020
23 GPR22 0000000000000000
24 GPR23 000000000000A859
25 GPR24 FFFFFFFFFFFFCF81
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 00000000359399A2
34 LR 0000000000000000
35 CTR FFFFFFFF3BCCFFFF
36 XER 0000000080000000
37