loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 168.out
1 GPR0 002AD6D6B223C54F
2 GPR1 000000003A27FFE9
3 GPR2 FFFFFFFFFFFFFFB5
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 000000000001C02F
9 GPR8 000000003FFFFF00
10 GPR9 0000000000000000
11 GPR10 148A000000000000
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFFFFFFFFF
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 FFFFFFFFFFFFFFE9
20 GPR19 0000000000000000
21 GPR20 000000000001C020
22 GPR21 FFFD4DD80001C02E
23 GPR22 0000000000000020
24 GPR23 FFFFFFFFC0000100
25 GPR24 0000000000000000
26 GPR25 0002B227FFFE3FD1
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000016
30 GPR29 0001FFFFFFED7FFF
31 GPR30 0000000000000000
32 GPR31
33 CR 000000003990DDD1
34 LR FFFFFFFFFFFFFFB5
35 CTR FFFFFFFFFFFFFFB5
36 XER 000000008003FF00
37