loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 169.out
1 GPR0 0000000000000040
2 GPR1 FFFFFFFFFFFFFFFF
3 GPR2 FFFFFFFFFFFFFFFF
4 GPR3 0000000000000001
5 GPR4 FFFFFFFFF3B204F2
6 GPR5 0000000000000000
7 GPR6 FFFFFFFDFBFFFFFF
8 GPR7 000000000001C028
9 GPR8 FFFFFFFFFFFFFFFE
10 GPR9 000000000007EF80
11 GPR10 FFFFFFFFF5555556
12 GPR11 0000000000000000
13 GPR12 0000000000000001
14 GPR13 0000000000FFEF85
15 GPR14 000000000000000D
16 GPR15 000000000001C020
17 GPR16 0000000000000040
18 GPR17 0000000000008008
19 GPR18 FFFFED5400012AC0
20 GPR19 0000000000000000
21 GPR20 FFFFFFFFFFFF9E37
22 GPR21 000000008003FFFF
23 GPR22 0000000000011BDF
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 FFFFFFFFFFFFFFFF
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000204000000
30 GPR29 0000000013B13B13
31 GPR30 0000000000038050
32 GPR31
33 CR 0000000059099375
34 LR 000000000000000A
35 CTR 0000000000000000
36 XER 00000000C00BFFFF
37