loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 19.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 0000000000000002
3 GPR2 0000000000000000
4 GPR3 1001E03FB0040003
5 GPR4 FFFFFFFFFFFFFFFE
6 GPR5 0000000000000002
7 GPR6 0380000002000000
8 GPR7 FFFFFFFFFBFFFFFF
9 GPR8 1001C02D30040003
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 FFFFFC0000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000007000
17 GPR16 0000000000000020
18 GPR17 0000000000000000
19 GPR18 FFFFFFFFCFFBFFFD
20 GPR19 000000000001C020
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFFFFF
23 GPR22 FFFFFFFFFFFFFFFD
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 FFFFFFFFCFFBFFFD
27 GPR26 1000E01690000002
28 GPR27 FFFFFFFFFFFFFFFF
29 GPR28 FFFFFFFFCFFBFFFE
30 GPR29 0000E01680000001
31 GPR30 FFFFFFFC00000000
32 GPR31
33 CR 000000009604A25A
34 LR 0000000000000000
35 CTR 0000000000017F8E
36 XER 00000000A0040000
37