loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 197.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 FFFFFFFFFFFFFFFF
3 GPR2 FFFFFFFFFFFFD57A
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000003
7 GPR6 00000000000079D1
8 GPR7 0000000000000000
9 GPR8 00000000FFFF0050
10 GPR9 00000000500B00B5
11 GPR10 FFFFFFFFFFFFFFFF
12 GPR11 0000000000000000
13 GPR12 0000000000000002
14 GPR13 0000000000000001
15 GPR14 0000000000000000
16 GPR15 0000000000004000
17 GPR16 0000000000000002
18 GPR17 000000000001C00B
19 GPR18 0000000000000000
20 GPR19 0000000000042800
21 GPR20 0000000000000000
22 GPR21 0000000000000003
23 GPR22 000000000001C02A
24 GPR23 FFFFFFFFFFFBD7FF
25 GPR24 00000000010A0000
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFFFFE3FD4
28 GPR27 0000000000000000
29 GPR28 FFFFFFFFFFFFFFF0
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 00000000900B00F5
34 LR 000000000001C020
35 CTR 000000000001C020
36 XER 00000000C0080000
37