loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 209.out
1 GPR0 0000060000000620
2 GPR1 000000000001C01C
3 GPR2 FFFFFFFFFFFFC490
4 GPR3 0000000000000000
5 GPR4 00000000FFFFFF9B
6 GPR5 FFFFFFFFFFFFFFE0
7 GPR6 FFFFFF9BFFFFFF9B
8 GPR7 FFFFFFFFFFFFFFFF
9 GPR8 FFFFFFFFFFFFFFFF
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000300
13 GPR12 0000000000000300
14 GPR13 000000000001CE9E
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 FFFFFFFFFFFF9EB3
22 GPR21 000E48400E48400E
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000006451B2F700
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000020
31 GPR30 00000000217090FD
32 GPR31
33 CR 000000000070000D
34 LR 0000000000000000
35 CTR FFFFFFFFFFFFFFFF
36 XER 0000000080000000
37