loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 219.out
1 GPR0 0000000000000001
2 GPR1 0000000000000000
3 GPR2 0000000000000002
4 GPR3 000000000F06ED38
5 GPR4 00000000000161B2
6 GPR5 F7F8F8F7F8FFFBF6
7 GPR6 0000000000000000
8 GPR7 000000000783769C
9 GPR8 0000000000000000
10 GPR9 4000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000002
13 GPR12 000000000001C020
14 GPR13 0000000000000002
15 GPR14 0000000000008006
16 GPR15 00000000390D0FD0
17 GPR16 0000000000000000
18 GPR17 000000000001C020
19 GPR18 0000000000000000
20 GPR19 000000000001C00C
21 GPR20 FFFFFFFFFFFE3FE0
22 GPR21 000000000001C01F
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 FFFFFFFFFFFFC020
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 00000000003FFFFF
30 GPR29 000000000000B5A1
31 GPR30 0000000000007008
32 GPR31
33 CR 00000000990D0FD0
34 LR FFFFFFFF07FE4A96
35 CTR 0000000000000000
36 XER 00000000A0057FDF
37