loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 24.out
1 GPR0 0000000000000000
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000001
8 GPR7 0000000000000000
9 GPR8 00000000200C0000
10 GPR9 0000000000000000
11 GPR10 FFFFFFFFFFFFA0E7
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 000000000001C020
20 GPR19 0000000000000000
21 GPR20 0000000000006618
22 GPR21 0000000000000000
23 GPR22 FFFFFFFFFFFFFFFF
24 GPR23 FFFFFFFFFFFFD591
25 GPR24 0000000000000700
26 GPR25 FFFFFFFFFFFF99E7
27 GPR26 0000000000000700
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000039957E30
34 LR 0000000000000700
35 CTR FFFFFFFFFFFFFFFE
36 XER 0000000080000000
37