loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 244.out
1 GPR0 0000000000000003
2 GPR1 0000000000000000
3 GPR2 0000000000000034
4 GPR3 0000000000000000
5 GPR4 0000000400000004
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 FFFFFFFFFFFFFFFF
9 GPR8 0000000000000001
10 GPR9 0000000000000000
11 GPR10 0000000000000001
12 GPR11 FFFFF807FFFFFFEC
13 GPR12 00000000A005C021
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000001
18 GPR17 0000000000000033
19 GPR18 0000000000000542
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFFFFF
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000009A74616
27 GPR26 0000000000000001
28 GPR27 FFFFFFFFFFFFFFFD
29 GPR28 0000000000000000
30 GPR29 FFFFFFFFFFFFFFFF
31 GPR30 FFFFF807FFFFFFF8
32 GPR31
33 CR 0000000030095F09
34 LR 0000000000000000
35 CTR FFFFF807FFFFFFF8
36 XER 00000000A005C021
37