loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 264.out
1 GPR0 3000000030000000
2 GPR1 3000000030000000
3 GPR2 FFFFFFFFFFFFFFFF
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 00000000300D95CD
7 GPR6 0000000000000040
8 GPR7 FFFFFFFFFFFFFFFF
9 GPR8 000000000001EA49
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 00000000FFFFFFFF
13 GPR12 000000000001C020
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 00000000C8C10000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 00000000300D95CD
23 GPR22 0000000000000000
24 GPR23 FFFFFFFFFFFFFFFF
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFFFFFFFFF
28 GPR27 000000000000001B
29 GPR28 0000000000000020
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000050009000
34 LR 0000000000000140
35 CTR 0000000000000000
36 XER 0000000080010690
37