loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 297.out
1 GPR0 00006A000001F5FF
2 GPR1 000000000001C020
3 GPR2 0000000000000000
4 GPR3 FFFFFFFFFFFFFFFF
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 FFFFFFFFFFFFFFFA
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFFFBFA
10 GPR9 FFFFFFFFFFFFFFFE
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 000000000000B74D
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 00000000BE3C0000
23 GPR22 0000000000000000
24 GPR23 FFFFFFFFFFFFFFFF
25 GPR24 0000000000000035
26 GPR25 FFFFFFFF41C3FFFE
27 GPR26 0000000000000000
28 GPR27 0000000000000020
29 GPR28 0000000000000000
30 GPR29 FFFFFFFFFFFFFF00
31 GPR30 0000000000000040
32 GPR31
33 CR 000000009A208720
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 00000000A0040000
37