loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 319.out
1 GPR0 FFFFFFFFFFFFFFC0
2 GPR1 0000000000000000
3 GPR2 000000000001C024
4 GPR3 FFFFFFFFCE2CA736
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 FFFFFFFFFFFE3FDF
8 GPR7 000000000000E9D9
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 000000000000384B
12 GPR11 000000000000384C
13 GPR12 0000000000000000
14 GPR13 000000000001C065
15 GPR14 0000000000000000
16 GPR15 FFFFFFFFFFFE3FD3
17 GPR16 FFFFFFFFFFFE384C
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 0000000000000000
20 GPR19 000000000001C024
21 GPR20 000000000000384C
22 GPR21 FFFFFFFFFFFE3FDF
23 GPR22 FFFFFFFFCE2CFFF0
24 GPR23 0000000000000000
25 GPR24 0000000000000040
26 GPR25 000000000001C00C
27 GPR26 0000000000000000
28 GPR27 FFFFFFFFFFFFFFFF
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000040
32 GPR31
33 CR 000000005155496D
34 LR FFFFFFFFFFFFFFFF
35 CTR FFFFFFFFFFFFFFFF
36 XER 0000000080008274
37