loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 323.out
1 GPR0 0000000000000000
2 GPR1 0000000000000003
3 GPR2 0000000000000000
4 GPR3 0000000000000040
5 GPR4 0000000000000000
6 GPR5 0000000000000003
7 GPR6 0000002000000017
8 GPR7 FFFFFFFFFFFFFFFF
9 GPR8 FFFFFFFFFFFFFFFF
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000017
13 GPR12 FFFFFFFFFFFFFFFF
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 FFFFFFFFFFFFFFFF
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000020
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 FFFFFFFFFFFFFFFF
26 GPR25 0000000000000000
27 GPR26 0000000000000003
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 FFFFFFFFFFFFE6F4
31 GPR30 0000000000000000
32 GPR31
33 CR 000000003F0FD09D
34 LR 0000000000000020
35 CTR 0000000000000000
36 XER 0000000080000000
37