loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 326.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 0000000000000000
3 GPR2 000000007F2C0000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000216CA0000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFFFFFF
10 GPR9 00000000000086C0
11 GPR10 000000003388C408
12 GPR11 000000000003F800
13 GPR12 FFFFFFFFFFFFDC04
14 GPR13 FFFFFFFFFFFFFFFF
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 FFFFFFFFFFFFFFFF
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000001
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 FFFFFFFFFFFFFFFF
30 GPR29 FFFFFFFFFFFFFF00
31 GPR30 FFFFFFFFFFFFFFFF
32 GPR31
33 CR 000000003088C408
34 LR 0000000000000001
35 CTR 00000000000086C0
36 XER 0000000080000000
37