loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 338.out
1 GPR0 0000000000000018
2 GPR1 000000009F05179A
3 GPR2 00000000D876A401
4 GPR3 FFFFFFFFFFFFFFC2
5 GPR4 0000000000000001
6 GPR5 0000000000000000
7 GPR6 FFFFFFFFFFFFFFFF
8 GPR7 FFFFFFFFFFFFF730
9 GPR8 0000000000000000
10 GPR9 0000000000007B04
11 GPR10 0000000000000020
12 GPR11 0000000000000005
13 GPR12 FFFFFFFFFFFE3EE4
14 GPR13 000000000000000D
15 GPR14 0000000000000000
16 GPR15 000000000001C0FD
17 GPR16 0000000000005F78
18 GPR17 FFFFFFFFFFFFFFFE
19 GPR18 000000000001C11C
20 GPR19 0000000000000020
21 GPR20 FFFFFFFFFFFFFFFE
22 GPR21 0000000000000000
23 GPR22 FFFFFFFFFFFFFFF3
24 GPR23 000000000000000F
25 GPR24 FFFFFFFFFFFE3F03
26 GPR25 FFFFFFFFFFFFF730
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 00000000D876C018
30 GPR29 0000000000000000
31 GPR30 00000000FFFE3EE4
32 GPR31
33 CR 000000005D05175A
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 00000000C00B0000
37