loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 346.out
1 GPR0 0000000000006A92
2 GPR1 000000000001C020
3 GPR2 0000000000000000
4 GPR3 FFFFFFFFFFFFFFFF
5 GPR4 FFFFFFFFFFFFFFFE
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFFFFFF
10 GPR9 0000000000000000
11 GPR10 07FFFFFFFFFFFFFF
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFFFFFFFFF
14 GPR13 FFFFFFFFFFFFFFFF
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 FFFFFFEFFFFFFFEF
18 GPR17 FFFFFFFFFFFFBA3A
19 GPR18 0000000000000000
20 GPR19 0000000000000021
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000090000000
27 GPR26 0000000000000000
28 GPR27 0000000000000018
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 000000005005092D
34 LR FFFFFFFFFFFFFFFF
35 CTR 0000000000000000
36 XER 0000000080020021
37