loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 356.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000080000020
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 00000000000035AA
9 GPR8 000000000000617B
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFFFFE140E
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000008
20 GPR19 000000000000003E
21 GPR20 FFFFC28000000000
22 GPR21 0000000000000000
23 GPR22 00000007FFFFFFC0
24 GPR23 0000000000000003
25 GPR24 0000000000000020
26 GPR25 FFFFFFFFFFFFFFFF
27 GPR26 000000000001C034
28 GPR27 0000000000000000
29 GPR28 FFFFFFF800000000
30 GPR29 0000000000000000
31 GPR30 FFFFFFFFFFFE3FCC
32 GPR31
33 CR 000000003F353195
34 LR 0000000000000000
35 CTR FFFFFFFFFFFE3FC2
36 XER 0000000080000020
37