loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 357.out
1 GPR0 0000000000000800
2 GPR1 000000000001C020
3 GPR2 0000000000000000
4 GPR3 00000000238E0000
5 GPR4 0C2BE84400000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 00000000238E0000
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000020
12 GPR11 FFFFFFFFFFFF8CD0
13 GPR12 FFFFFFFFFFFFFFFF
14 GPR13 0000000000000000
15 GPR14 0000491F1A88041D
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 FFFFFFFFFFFFFFFF
19 GPR18 0000000000000000
20 GPR19 0000000000000003
21 GPR20 0000000000007330
22 GPR21 0000000000000000
23 GPR22 0000000000038040
24 GPR23 0000000000038043
25 GPR24 FFFFFFFFFFFFFFFC
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFFFFFFFFE
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 000000000000003A
32 GPR31
33 CR 000000005009B89A
34 LR 0000000000000020
35 CTR 0000000000000000
36 XER 0000000080000040
37